Sidewall Spacer Structure for Low-Capacitance Source/Drain Epitaxy

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to create smaller and more complex circuits while minimizing contact area between source/drain epitaxial structures and channel layers, which affects device performance and efficiency.

Innovation Solution

The implementation of etched-back sidewall spacers on opposite sides of source/drain epitaxial structures, which create extra space for inner-spacer residues, reducing contact area and enlarging the window for growing the source/drain epitaxial structures, thereby enhancing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If source/drain epitaxial structures are grown directly on channel layers, then device functionality is achieved, but contact area is too large causing increased parasitic capacitance

Engineering Contradiction:
Improveparasitic capacitanceVSAvoiddevice performance
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent introduces sidewall spacers that segment the contact area between source/drain epitaxial structures and channel layers into distinct regions. The spacers create a physical separation that divides the originally continuous contact interface, thereby reducing the effective contact area and parasitic capacitance while maintaining necessary electrical connections through controlled epitaxial growth regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sidewall spacers act as intermediary structures between the source/drain epitaxial structures and the channel layers. These spacers mediate the interaction by providing a controlled interface that reduces direct contact area, thus lowering parasitic capacitance while still allowing the epitaxial structures to grow and establish proper electrical connectivity to the channel.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If circuit geometry is scaled down to increase functional density, then production efficiency improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improveproduction efficiencyVSAvoidgeometry size control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The sidewall spacers provide self-aligned features that serve as natural boundaries for epitaxial growth. The spacers are formed first, and then the source/drain epitaxial structures grow automatically confined by these spacer boundaries, eliminating the need for additional alignment steps and reducing manufacturing precision requirements despite scaled-down geometries.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The sidewall spacers are formed in advance before the epitaxial growth of source/drain structures. This preliminary action establishes the geometric boundaries and contact area limits beforehand, allowing subsequent epitaxial growth to proceed with relaxed precision requirements since the spacer structures already define the desired geometry constraints.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces parasitic capacitance and improves device efficiency by allowing controlled growth of source/drain epitaxial structures, resulting in smaller and more complex circuits with improved performance.

Implementation Method 1

This approach reduces parasitic capacitance and improves device efficiency

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Implementation Method 2

epitaxially growing a source/drain structure over the substrate and in contact with the channel layer of the remaining portion of the fin structure

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS12484246B2Method of manufacturing a semiconductor device including forming a sidewall spacer on a sidewall of a channel structure
Publication Date: 2025.11.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12484246B2 patent drawing
  • US12484246B2 patent drawing
  • US12484246B2 patent drawing

AI summary

A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a sidewall spacer. The channel layer is over a substrate. The gate structure wraps around the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The sidewall spacer is on a sidewall of the first source/drain epitaxial structure and includes a first dielectric layer and a second dielectric layer over the first dielectric layer and in contact with first source/drain epitaxial structure. The first dielectric layer and the second dielectric layer include different materials.