Sidewall Spacer Structure for Gap-Free Multi-Channel Fin Isolation
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Solution Overview
Problem
As minimum feature size reduces in semiconductor manufacturing, it becomes challenging to form inner spacers around all channels without gaps in multi-channel transistors, affecting the integration density and performance of semiconductor devices.
Innovation Solution
A method is developed to form a sidewall spacer by filling a trench between a hybrid fin and a semiconductor fin structure, comprising fin sidewall spacer portions connected by a gate sidewall spacer portion, providing uniform protection and eliminating gaps between inner and sidewall spacers through a series of epitaxial growth, etching, and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional recessing and dielectric deposition is used to form inner spacers, then the process is simple and straightforward, but gaps form between inner spacers and sidewall spacers, compromising isolation reliability
Solution Approach 1:
The patent merges the formation of inner spacers and sidewall spacers into a single continuous dielectric structure by using conformal deposition that extends from the channel sidewalls through the trench region to the top surface, eliminating gaps between previously separate spacer components
Solution Approach 2:
The patent performs preliminary trench filling with dielectric material before final planarization, ensuring that the spacer material is deposited in advance to fill gaps and provide continuous isolation, with excess material later removed by CMP to achieve the final planar surface
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but forming inner spacers around all channels without gaps becomes increasingly challenging
Solution Approach 1:
The patent extends the spacer formation from a two-dimensional planar deposition to a three-dimensional conformal coating that follows the complex topography including channel sidewalls, trench regions, and top surfaces, ensuring uniform coverage across multiple height levels and eliminating gaps that plague planar approaches at scaled dimensions
Solution Approach 2:
The patent replaces mechanical recessing and separate deposition steps with a unified conformal deposition process that automatically adapts to the underlying topography, using the deposition mechanism itself to ensure continuous material coverage rather than relying on precise mechanical alignment of separate steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform coverage and improved isolation around semiconductor channel layers, preventing leaks and enhancing the integration density and performance of semiconductor devices by maintaining consistent spacer thickness and geometry.
Implementation Method 1
The semiconductor materials are recessed from the top surface to a first depth to form trenches between adjacent fin structures
Implementation Method 2
depositing a dielectric material in place of the recessed semiconductor materials
Data Source
AI summary
Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.