Sidewall Spacer Gate Trench MOSFET for Reduced Gate Charge
Solution Overview
Problem
Trench type power semiconductor devices face challenges in reducing gate-drain charge and gate charge due to difficulties in controlling polysilicon gate recess depth and void formation, which affects threshold voltage and leakage current stability.
Innovation Solution
The use of sidewall spacer gates formed by depositing a thin layer of doped polysilicon in gate trenches and etching until the bottom surface is exposed, with a silicide layer covering the outer surfaces to reduce gate resistance, allowing for minimal overlap with the drain epi region and increased trench width/depth without sacrificing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick polysilicon gate mass is used to fill gate trenches, then gate electrodes can fully overlap channel region, but gate-drain charge increases and polysilicon recess depth control becomes difficult
Solution Approach 1:
The patent extracts the polysilicon gate material from the bottom portion of the gate trench, creating a void space. This is achieved by depositing polysilicon and then selectively removing it from the trench bottom while retaining it on the sidewalls, thereby reducing gate-drain charge while preserving channel overlap functionality through the sidewall spacer gates.
Solution Approach 2:
The patent transitions from a traditional planar gate electrode filling the trench bottom to a three-dimensional sidewall spacer gate structure. The gate electrode is repositioned from occupying the trench bottom (2D plane) to wrapping around the channel region on the sidewalls (3D structure), enabling effective channel control with reduced gate-drain overlap.
2Quantity of substance
If gate trenches are made thin to reduce gate electrode size, then gate-drain charge decreases, but trench cleaning becomes difficult leading to defects
Solution Approach 1:
The patent performs preliminary widening of the gate trench before polysilicon deposition. By pre-expanding the trench width, sufficient space is created for effective cleaning operations and subsequent polysilicon deposition, ensuring that the trench can be properly prepared without compromising the final gate-drain charge reduction goal.
3Quantity of substance
If gate insulation layer is made thick at trench bottom to reduce gate-drain charge, then overlap is reduced, but threshold voltage increases due to thick insulation
Solution Approach 1:
The patent applies different gate insulation layer thicknesses at different locations: a thinner insulation layer at the trench bottom to maintain low threshold voltage, and a thicker insulation layer on the sidewalls to reduce gate-drain charge. This spatial variation in insulation thickness allows simultaneous optimization of both parameters.
4Ease of manufacture
If polysilicon is deposited to fill gate trenches, then gate electrodes form, but voids form in polysilicon affecting threshold voltage and leakage current stability
Solution Approach 1:
The patent performs preliminary widening of the gate trench before polysilicon deposition. This pre-expansion creates adequate space for complete and uniform polysilicon filling, preventing void formation. The wider trench allows the polysilicon deposition process to proceed without trapping air pockets, thereby ensuring threshold voltage and leakage current stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate-drain charge and gate charge, improves device efficiency, and minimizes void-related instabilities, enabling better control over polysilicon recess depth and reduced trench defects.
Implementation Method 1
a silicide layer covers the full outer surfaces of the spacer gate to substantially reduce the gate resistance (Rg) of the gate
Implementation Method 2
A gate insulation layer 224 lines the sidewalls and bottom surface of each gate trench 212
Data Source
AI summary
A semiconductor power device includes a semiconductor body with a plurality of gate trenches formed therein. Disposed within each gate trench is a spacer gate that extends along at least a portion of the sidewalls of the gate trench but not along at least a portion of the bottom surface of the trench. The spacer gate of each gate trench may also include a layer of silicide along outer surfaces thereof. The semiconductor body may include a channel region and each gate trench may extend through the channel region and into the semiconductor body. Formed at the bottom of each gate trench within the semiconductor body may be a tip implant of the same conductivity as the semiconductor body. In addition, a deep body implant of the same conductivity as the channel region may be formed at the base of the channel region.