Sidewall Spacer Formation for IC Line Width Control
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Solution Overview
Problem
Photolithographic processes introduce random variations in the width and spacing of lines in integrated circuit devices, leading to performance variability and reliability issues due to line edge roughness and uneven thermal stress, which affect manufacturing yield.
Innovation Solution
A sequential sidewall spacer formation process is used to form alternating sets of spacers on a semiconductor substrate, where one set defines the etch mask to create uniform trenches and lines, independent of photolithographic variations, by iteratively depositing conformal layers and performing directional etches, allowing control over line width and spacing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processes are used to pattern lines, then manufacturing capability is achieved, but line width and spacing variations occur due to line edge roughness
Solution Approach 1:
The patent segments the patterning process into multiple steps: first forming an initial mask pattern, then using it to create spacer structures that define the final line positions. This segmentation allows the critical dimensions to be determined by the spacer thickness rather than the initial photolithographic pattern, reducing LER impact
Solution Approach 2:
The patent introduces spacer structures as intermediary elements between the photolithographically formed mask and the final patterned lines. These spacers act as a mediator that transfers the pattern while filtering out LER variations, as the spacer thickness is controlled by conformal deposition rather than direct lithography
2Manufacturing precision
If parallel lines of resist are used as etch mask, then pattern transfer is achieved, but random variations in spacing between adjacent lines occur
Solution Approach 1:
The patent segments the spacing control function from the line formation function. The initial mask provides line positions, while separately formed spacer structures provide uniform spacing. This segmentation allows independent optimization of each function and eliminates the coupling of spacing variations with line width variations
Solution Approach 2:
The patent changes the controlling parameter for spacing from photolithographic dimensions to deposition thickness. By controlling spacer thickness through conformal deposition processes, the spacing between lines is determined by a parameter (film thickness) that can be controlled with much tighter tolerances than photolithographic dimensions
3Productivity
If feature sizes are shrunk to increase density, then device capacity increases, but photolithographic variations become a greater percentage of critical dimension
Solution Approach 1:
The patent transitions from two-dimensional photolithographic patterning to a three-dimensional spacer formation approach. By depositing conformal layers that wrap around the initial mask structures and then anisotropically etching, the critical dimension is determined by vertical film thickness rather than horizontal lithographic resolution, effectively moving the precision requirement to another dimension where better control exists
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process results in high-density integrated circuit devices with reduced line width and edge roughness variations, improving performance uniformity and yield by minimizing the impact of photolithographic process variations, and ensuring consistent thermal stresses across the device.
Implementation Method 1
iteratively depositing a conformal layer of material having a thickness on a sidewall
Implementation Method 2
performing a directional etch process which leaves the material on the sidewall
Implementation Method 3
The first set of sidewall spacers comprise a material, such as silicon oxide, that can be selectively etched relative to a material, such as silicon nitride, of the second set of sidewall spacers
Data Source
AI summary
An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.