Sidewall Spacer Image Transfer Without Anti-Reflective Coating
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Solution Overview
Problem
Conventional sidewall image transfer processes in semiconductor manufacturing face issues such as resist footing, tapered mandrel profiles, non-selective etching of anti-reflective coating layers, leading to critical dimension variations, line edge roughness, and pitch walking due to uneven ARC layer thickness.
Innovation Solution
The method involves forming sidewall spacers directly on a hard-mask layer, using a planarization layer and directional etching to create mandrels, and transferring the image pattern from the hard-mask layer to the substrate, with a burn-off process to remove spacers, avoiding the use of anti-reflective coating layers to maintain precise control over critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If anti-reflective coating layer is used in conventional SIT process, then mandrel formation is facilitated, but etching selectivity is lost causing CD variations and pitch walking
Solution Approach 1:
The patent removes the anti-reflective coating layer from the process flow, forming mandrels directly on the hard mask layer. This extraction eliminates the source of etching non-selectivity and the associated CD variations while maintaining mandrel formation capability through direct lithographic patterning on the hard mask.
Solution Approach 2:
The patent segments the process into distinct steps: forming mandrels directly on hard mask, depositing spacer material, and performing etch-back. This segmentation allows each step to be optimized independently, with the etch-back process being highly selective to the spacer material while leaving the hard mask and mandrels intact.
2Ease of manufacture
If spacer etch-back is performed on ARC layer, then spacer formation is completed, but ARC layer thickness varies causing line edge roughness
Solution Approach 1:
The patent introduces a planarization layer as an intermediary between the hard mask and the spacer etch-back process. This planarization layer provides a uniform surface for spacer deposition and serves as a sacrificial layer during etch-back, ensuring consistent spacer thickness and eliminating line edge roughness caused by varying ARC layer thickness.
Solution Approach 2:
The patent changes the material parameter of the layer underlying the spacers from anti-reflective coating to planarization layer. This parameter change ensures that the etch-back process is highly selective to the spacer material while the planarization layer provides a uniform thickness that prevents line edge roughness.
3Productivity
If conventional SIT process is used, then device density is increased, but resist footing and tapered profiles degrade pattern fidelity
Solution Approach 1:
The patent performs preliminary planarization before mandrel formation by depositing a planarization layer on the hard mask. This preliminary action creates a perfectly flat surface that eliminates resist footing and tapered profiles during subsequent lithographic patterning, ensuring high pattern fidelity while maintaining the density benefits of SIT.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances control over critical dimensions and reduces line edge roughness and pitch walking by ensuring uniformity and selectivity in the etching process, improving the fidelity of the device pattern transfer.
Implementation Method 1
performing directional etching of the conformal layer to create the set of sidewall spacers
Implementation Method 2
a burn-off process to remove spacers
Data Source
AI summary
An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.