Sidewall Spacer Morphology Control via Transition Layer Etching

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Solution Overview

Problem

Existing semiconductor fabrication methods, such as self-aligned double patterning and quadra patterning, result in undesired device performance due to manufacturing limitations, leading to large surface roughness and apex angles in sidewall spacers, which affect pattern precision and critical dimension.

Innovation Solution

A method involving the formation of initial sidewall spacers followed by a modification treatment to create a transition layer, which is then removed using atomic layer etching, to improve top morphology and reduce surface roughness, resulting in sidewall spacers with desired profiles and reduced critical dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If self-aligned double patterning or quadra patterning is used to reduce critical dimension, then pattern density increases, but surface roughness and apex angles in sidewall spacers worsen

Engineering Contradiction:
Improvecritical dimensionVSAvoidsidewall spacer profile
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

A transition layer is formed on the sidewall spacers before the final etching process. This preliminary action modifies the spacer surface morphology in advance, enabling subsequent removal of the transition layer to achieve desired profile characteristics (rounded top, reduced roughness) while maintaining the critical dimension control provided by SADP/SAQP

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The transition layer acts as an intermediary substance between the initial sidewall spacer and the final patterned structure. It mediates the morphology transformation by being deposited on the spacer, modifying its surface properties, and then being selectively removed to reveal the improved spacer profile underneath

Inventive Principle:
Principle #24Intermediary (Mediator)

2Shape

If modification treatment process is applied to improve top morphology, then surface roughness reduces, but process complexity increases

Engineering Contradiction:
Improvetop morphologyVSAvoidfabrication process
Core Design Contradiction:
ShapeVSDevice complexity

Solution Approach 1:

The modification treatment process changes the physical and chemical parameters of the sidewall spacer surface by forming a transition layer with different material composition and morphology. This parameter change enables controlled modification of surface roughness and top shape through subsequent selective removal, achieving improved morphology without requiring complex mechanical or chemical polishing processes

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the top morphology and reduces surface roughness of sidewall spacers, improving semiconductor structure performance by achieving smaller dimensions and more precise pattern transfer.

Implementation Method 1

modifying the plurality of initial sidewall spacers includes a plasma treatment process

Methodology Applied
Scientific EffectPlasma deposition: Plasma Enhanced Chemical Vapour Deposition

Implementation Method 2

removing the transition layer includes performing an atomic layer etching process

Methodology Applied
Scientific EffectAtomic layer etching:

Implementation Method 3

passivating the transition layer to convert at least a portion of the transition layer into a passivated transition layer using a passivation gas to react with a surface of the transition layer

Methodology Applied
Scientific EffectChemical reaction (passivation): Chemical Bonding

Implementation Method 4

etching the passivated transition layer using an etching gas to react with the passivated transition layer to remove the passivated transition layer

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS11393685B2Semiconductor structure and fabrication method thereof
Publication Date: 2022.07.19 SEMICON MFG INT (SHANGHAI) CORP
  • US11393685B2 patent drawing
  • US11393685B2 patent drawing
  • US11393685B2 patent drawing

AI summary

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.