Sidewall Spacer Patterning for Semiconductor Overlay Accuracy
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Solution Overview
Problem
Current semiconductor manufacturing processes face limitations in reducing the dimension of electronic elements due to optical lithography constraints, which hinder the increase in the number of elements per unit area on a wafer substrate, and existing methods are not effective in producing two-dimensional structures with high overlay accuracy and throughput.
Innovation Solution
A patterning method involving the formation of a target layer and a lining layer with rectangular blocks in a checkerboard disposition, followed by the creation of sidewall spacers and their use as etching masks to achieve precise pattern transfer and reduce the dimension of electronic elements, enhancing overlay accuracy and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical lithography is used to reduce the dimension of electronic elements, then the resolution of pattern transfer is improved, but the overlay accuracy cannot be controlled well and the dimension limitation is reached
Solution Approach 1:
The patterning process is divided into multiple steps: first forming a mandrel layer with initial patterns, then forming sidewall spacers on the mandrels, and finally using the spacers as masks for subsequent etching. This segmentation allows each step to be optimized independently, achieving both small dimensions and high overlay accuracy
Solution Approach 2:
The invention transitions from two-dimensional planar patterning to three-dimensional sidewall spacer formation. By utilizing the vertical dimension to create spacers on the sidewalls of mandrels, the method achieves self-aligned patterning that improves overlay accuracy while enabling smaller feature dimensions
2Productivity
If the quantity of electronic elements on a unit area is increased, then the operation speed is faster and power is lower, but the dimension reduction faces bottlenecks
Solution Approach 1:
The sidewall spacers are formed through self-aligned processes where the spacer material automatically deposits on the sidewalls of the mandrels. This self-alignment eliminates the need for additional alignment steps, enabling high-density patterning with maintained precision
Solution Approach 2:
The invention changes the physical parameters of the patterning process by using different materials for mandrels and spacers, and by controlling the thickness of spacer layers through atomic layer deposition (ALD). These parameter changes enable precise control of feature dimensions while increasing element density
3Manufacturing precision
If other lithography processes such as E-beam or EUV are used, then the dimension can be reduced further, but the throughput and material limitations occur
Solution Approach 1:
The invention replaces direct lithographic patterning with a self-aligned spacer-based approach. Instead of relying on high-resolution lithography tools (E-beam, EUV), the method uses conventional lithography combined with atomic layer deposition and etching processes, achieving similar or better resolution with higher throughput
Data Source
AI summary
A patterning method in a semiconductor manufacturing process includes the following steps. A base is provided. A target layer and a lining layer are sequentially formed on the surface of the base. The lining layer is patterned to form a plurality of rectangular blocks. A sidewall spacer material layer is formed on the rectangular blocks and the target layer. Part of the sidewall spacer material layer is removed to form a sidewall spacer on the side wall of each of the plurality of rectangular blocks. The plurality of rectangular blocks is removed, and the sidewall spacer is used as a hard sheltering mask to etch and remove part of the target layer. The overlay accuracy is improved and the dimension of the electronic elements can be reduced so that a lot of two-dimension structures can be manufactured on the wafer substrate.