Sidewall Spacer Thickness Control in Memory Devices
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Solution Overview
Problem
The existing manufacturing methods for memory devices constrain the thickness of sidewall spacers in peripheral circuits due to their formation in conjunction with spacers in densely packed memory arrays, limiting the precision and depth of source/drain regions and increasing manufacturing costs.
Innovation Solution
A method is developed to form sidewall spacers with distinct thicknesses in memory device regions by depositing and etching dielectric layers, allowing for an L-shaped cross-section in peripheral circuits with a thicker spacer than in memory arrays, using a composite spacer structure with selectively etchable materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sidewall spacers are formed in conjunction with memory array spacers using the same process, then manufacturing cost is reduced, but the thickness of peripheral circuit spacers is constrained and cannot be optimized for precision source/drain formation
Solution Approach 1:
The patent divides the spacer formation process into two independent stages: first forming memory array spacers, then forming peripheral circuit spacers separately. This segmentation allows each region to have optimized spacer thickness independent of the other, resolving the contradiction between manufacturing simplicity and precision requirements.
Solution Approach 2:
The patent applies different spacer thicknesses to different regions: thinner spacers for memory arrays and thicker spacers for peripheral circuits. This local differentiation enables optimized source/drain formation in peripheral circuits while maintaining cost-effectiveness through the independent process sequence.
2Device complexity
If a single spacer thickness is used for both memory arrays and peripheral circuits, then the manufacturing process is simplified, but device variability increases and short channel effect is not optimized
Solution Approach 1:
The process is segmented into distinct formation steps for memory array spacers and peripheral circuit spacers, allowing independent optimization of each region's device characteristics while maintaining overall process manageability.
Solution Approach 2:
The patent changes the spacer thickness parameter between regions: thinner spacers for memory arrays and thicker spacers for peripheral circuits. This parameter differentiation reduces device variability and optimizes short channel effect without excessive process complexity.
3Manufacturing precision
If additional photolithographic processes are used to form different spacer thicknesses, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent forms a preliminary masking layer before spacer deposition that pre-defines the peripheral circuit regions. This preliminary action enables subsequent selective etching to create different spacer thicknesses without requiring additional photolithography steps, maintaining cost-effectiveness while achieving precision.
Solution Approach 2:
The masking layer serves as an intermediary element that enables differential spacer formation. By using this intermediate structure, the patent achieves precise thickness control through selective etching rather than through additional lithographic processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more precise formation of source/drain regions in peripheral circuits, reduces device variability, and improves the short channel effect while maintaining cost-effectiveness by avoiding additional photolithographic processes.
Implementation Method 1
depositing a first dielectric layer on the peripheral circuit region and the memory array region; depositing a second dielectric layer on the first dielectric layer
Implementation Method 2
depositing a first dielectric layer on the peripheral circuit region and the memory array region; depositing a second dielectric layer on the first dielectric layer
Implementation Method 3
etching the second dielectric layer to expose the first dielectric layer; etching the third dielectric layer in the memory array region to expose the second dielectric layer and the first dielectric layer
Data Source
AI summary
The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.