Sidewall Channel Transistor Structure for Small-Footprint Semiconductors
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving transistors with minute sizes, long channel lengths, favorable electrical characteristics, low power consumption, and high-definition displays while maintaining high reliability and productivity.
Innovation Solution
The semiconductor device incorporates a first and second insulating layer with a transistor structure that includes a semiconductor layer, gate insulating layer, and electrodes, where the semiconductor layer is in contact with the side surfaces of the insulating layers and electrodes, allowing for precise control of channel width and length, and multiple current paths to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the transistor size is reduced to increase definition and aperture ratio, then the pixel size can be reduced and definition can be increased, but the channel length becomes short which deteriorates electrical characteristics
Solution Approach 1:
The patent introduces a vertical dimension by forming an insulating layer with a side surface that extends vertically, and the semiconductor layer contacts this side surface. This vertical structure allows the channel length to extend in the vertical direction rather than only horizontally, enabling long channel length within a small planar footprint, thus resolving the contradiction between miniaturization and maintaining electrical characteristics.
Solution Approach 2:
The patent embeds the semiconductor layer within the opening of the insulating layer structure, where the semiconductor layer is surrounded by the insulating layer's side surface. This nested configuration allows the channel to form along the vertical side surface, achieving compact integration while maintaining sufficient channel length for good electrical characteristics.
2Reliability
If the channel length is increased to improve electrical characteristics, then the transistor size increases, but the pixel size and definition are compromised
Solution Approach 1:
The patent utilizes the vertical dimension by having the semiconductor layer contact the vertical side surface of the insulating layer. This allows the channel length to be extended vertically without increasing the horizontal footprint, enabling long channel length transistors to fit within small pixel areas, thus improving electrical characteristics without compromising definition.
3Ease of manufacture
If conventional transistor structures are used, then manufacturing is simpler, but the aperture ratio and definition cannot be sufficiently increased
Solution Approach 1:
The patent segments the transistor structure into distinct functional regions: the insulating layer with its opening and side surface, the semiconductor layer contacting the side surface, and the gate electrode. This segmentation allows each component to be optimized independently while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
Data Source
AI summary
A semiconductor device with a small occupation area is provided. The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor is provided over the first insulating layer and includes a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The second insulating layer includes an opening reaching the first insulating layer. The source electrode and the drain electrode are provided over the second insulating layer. The semiconductor layer is provided in contact with a side surface of the second insulating layer in the opening, a top surface of the first insulating layer in the opening, and side surfaces of the source electrode and the drain electrode. The gate insulating layer is positioned over the semiconductor layer, the source electrode, and the drain electrode. The gate electrode overlaps with the opening and is positioned over the gate insulating layer.