SiGe BiCMOS High-Resistivity Substrate Integration
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Solution Overview
Problem
Current RF front-end modules face challenges with integration complexity, manufacturing cost, component size, and reliability due to the use of different semiconductor technologies for various functional building blocks, which can lead to suboptimal performance and increased losses in signal transmission and harmonic generation.
Innovation Solution
The implementation of a high-resistivity substrate in SiGe BiCMOS technology integrates multiple functional building blocks onto a single die, reducing parasitic junction capacitance and substrate losses, and enhancing linearity and efficiency by using a high-resistivity layer underneath SiGe BiCMOS elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different semiconductor technologies are used for various functional building blocks, then device functionality is achieved, but integration complexity and manufacturing cost increase
Solution Approach 1:
The patent combines bipolar transistors, CMOS circuits, and passive devices onto a single silicon substrate using SiGe BiCMOS technology. This merging of different functional building blocks into one integrated circuit reduces integration complexity and manufacturing cost while maintaining diverse device functionality.
Solution Approach 2:
The silicon substrate with high-resistivity portion serves as a universal platform that can host multiple types of devices (bipolar transistors, CMOS circuits, passive devices) with different functional requirements. The high-resistivity substrate provides a common foundation that accommodates various device technologies simultaneously.
2Adaptability or versatility
If different semiconductor technologies are used for various functional building blocks, then device functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines bipolar transistors, CMOS circuits, and passive devices onto a single silicon substrate using SiGe BiCMOS technology. This merging of different functional building blocks into one integrated circuit reduces integration complexity and manufacturing cost while maintaining diverse device functionality.
3Ease of manufacture
If conventional substrate is used, then manufacturing is simplified, but parasitic junction capacitance and substrate losses increase
Solution Approach 1:
The patent applies a high-resistivity implant to create a high-resistivity portion in specific regions of the silicon substrate, particularly underneath bipolar transistors and passive devices. This localized modification reduces parasitic junction capacitance and substrate losses in critical areas while maintaining standard substrate properties elsewhere for manufacturing simplicity.
Solution Approach 2:
The patent changes the electrical resistivity parameter of the substrate by introducing a high-resistivity implant. This parameter change from conventional low-resistivity to high-resistivity substrate reduces parasitic junction capacitance and substrate losses, improving RF signal transmission and reducing harmonic generation.
4Area of moving object
If component integration is increased, then device size is reduced, but assembly complexity increases
Solution Approach 1:
The patent combines bipolar transistors, CMOS circuits, and passive devices onto a single silicon substrate using SiGe BiCMOS technology. This merging of different functional building blocks into one integrated circuit reduces integration complexity and manufacturing cost while maintaining diverse device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced component size, cost, and assembly complexity, while improving RF signal transmission and reducing harmonic signal generation, enabling more predictable and efficient RF circuit design that meets the requirements of emerging standards like 802.11ac.
Implementation Method 1
reducing parasitic junction capacitance and substrate losses
Implementation Method 2
At least a second portion of the top surface of the substrate may include a high-resistivity crystal-lattice-destroying implant
Implementation Method 3
The silicon substrate of the semiconductor die may include a low-resistivity epitaxial layer formed adjacent to a first portion of a top surface of the substrate
Implementation Method 4
the low-resistivity epitaxial layer includes material from an implanted sub-collector region of the transistor that has out-diffused during processing of the transistor
Data Source
AI summary
Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.