Relaxed SiGe Buffer with Group III-V Interlayer

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Solution Overview

Problem

The direct growth of group III-V semiconductor layers on silicon substrates is hindered by lattice mismatch, thermal expansion mismatch, and interfacial surface energy differences, leading to high defect densities in silicon germanium strain relaxed buffers, which degrade device performance.

Innovation Solution

A film stack comprising a group III-V interlayer, such as GaAsP or InGaP, and a group IV buffer layer of silicon and germanium is formed on a substrate, with the interlayer's composition adjusted to match the lattice constant of the buffer layer, reducing lattice mismatch and defect formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If group III-V semiconductor layers are directly grown on silicon substrates, then device fabrication can proceed, but high defect densities occur due to lattice mismatch, thermal expansion mismatch, and interfacial surface energy differences

Engineering Contradiction:
Improvedirect growth capabilityVSAvoiddefect density
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A group III-V interlayer (InGaP or GaAsP) is introduced between the silicon substrate and the group IV buffer layer. This interlayer acts as an intermediary that reduces lattice mismatch and thermal expansion mismatch, thereby lowering defect density in the buffer layer while enabling direct growth on silicon substrates.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The composition of the group III-V interlayer is optimized by adjusting the concentration of indium or gallium and phosphorus to match the lattice constant of the overlying group IV buffer layer. This parameter optimization reduces misfit dislocations and improves layer quality.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If silicon germanium strain relaxed buffers are formed on active layers, then a foundation is provided for device growth, but defect densities greater than 10,000 cm−2 are created which cause defective channel layers

Engineering Contradiction:
Improvebuffer layer formationVSAvoiddefect density
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The group III-V interlayer serves as a mediator between the silicon substrate and the silicon germanium buffer layer, reducing the lattice mismatch and thermal expansion mismatch that would otherwise cause high defect densities in the buffer layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

A composite structure consisting of a group III-V interlayer (InGaP or GaAsP) and a group IV buffer layer (silicon and germanium) is formed on the silicon substrate. This composite material approach allows optimization of each layer's properties to achieve low defect density in the buffer layer.

Inventive Principle:
Principle #40Composite materials

3Reliability

If the interlayer's composition is adjusted to match the lattice constant of the buffer layer, then lattice mismatch and defect formation are reduced, but process complexity increases

Engineering Contradiction:
Improvelattice matching qualityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The composition parameters of the group III-V interlayer (indium or gallium concentration, phosphorus concentration) are optimized to achieve lattice constant matching with the group IV buffer layer. This parameter control reduces misfit dislocations while maintaining a manageable process through systematic composition adjustment.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in improved quality and performance of relaxed silicon germanium buffer layers, reducing defect densities and enabling smoother, thinner films with reduced strain, thereby enhancing the integration and performance of active device layers on silicon substrates.

Implementation Method 1

lattice mismatch, thermal expansion mismatch, and differences in interfacial surface energy between group III-V layers and the silicon substrate

Methodology Applied
Scientific EffectLattice mismatch:

Implementation Method 2

lattice mismatch, thermal expansion mismatch, and differences in interfacial surface energy between group III-V layers and the silicon substrate

Methodology Applied
Scientific EffectThermal expansion mismatch: Thermal Expansion

Implementation Method 3

lattice mismatch, thermal expansion mismatch, and differences in interfacial surface energy between group III-V layers and the silicon substrate

Methodology Applied
Scientific EffectInterfacial surface energy: Surface Tension

Implementation Method 4

silicon germanium strain relaxed buffers (SRBs) may be formed on active layers to provide a foundation

Methodology Applied
Scientific EffectStrain relaxation: Stress Relaxation

Data Source

PatentUS10125415B2Structure for relaxed SiGe buffers including method and apparatus for forming
Publication Date: 2018.11.13 APPLIED MATERIALS INC
  • US10125415B2 patent drawing
  • US10125415B2 patent drawing
  • US10125415B2 patent drawing

AI summary

Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.