SiGe Buffer Layer Conformity via High-Pressure Epitaxy

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor processes, the SiGe buffer layer formed under low pressure is non-conformal and thin at the lower sidewall, making it a weak point for dislocation and surface breaking, while increasing its thickness at the bottom compromises the depth of the strain-inducing SiGe layer.

Innovation Solution

A method involving a first epitaxy process under pressure higher than 65 torr to form a buffer layer with a specific thickness ratio on the sidewall to bottom, and a second epitaxy process to form a semiconductor compound layer, ensuring increased conformity without sacrificing strain depth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the buffer layer thickness at the lower sidewall is increased to prevent breaking through, then the reliability is improved, but the depth of the semiconductor compound layer is reduced

Engineering Contradiction:
Improveprevention of dislocation breaking throughVSAvoiddepth of semiconductor compound layer
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent applies local quality by forming a buffer layer with spatially varying thickness - thicker at the lower sidewall (ratio 0.4-0.8) to prevent dislocation breaking through, and thinner at the bottom to maintain compound layer depth. This non-uniform thickness distribution addresses different reliability needs at different locations within the cavity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the pressure parameter from low pressure (20 torr) to high pressure (65-120 torr) during epitaxial growth. This parameter change transforms the buffer layer formation from non-conformal to conformal, enabling precise control of thickness distribution and resolving the contradiction between sidewall protection and depth maintenance.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If low pressure epitaxy is used to form the buffer layer, then the manufacturing process is simpler, but the conformity of the buffer layer is poor

Engineering Contradiction:
Improvesimplicity of epitaxy processVSAvoidconformity of buffer layer thickness
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent changes the pressure parameter from low pressure (20 torr) to high pressure (65-120 torr) during epitaxial growth. This parameter change transforms the buffer layer formation from non-conformal to conformal, enabling precise control of thickness distribution and resolving the contradiction between sidewall protection and depth maintenance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the conformity of the SiGe buffer layer, preventing dislocation breaking through without increasing the bottom thickness, thus maintaining sufficient strain induction.

Implementation Method 1

A first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

A first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

A second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 4

A second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS9214551B2Method for fabricating semiconductor device, and semiconductor device made thereby
Publication Date: 2015.12.15 UNITED MICROELECTRONICS CORP
  • US9214551B2 patent drawing
  • US9214551B2 patent drawing

AI summary

A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.