SiGe Conduction Channel Formation via Germanium Condensation
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Solution Overview
Problem
Current MOS technologies face challenges in forming ultra-thin silicon germanium conduction channels that are compatible with thin body devices and achieving precise control over the insulating oxide layer in the gate stack, particularly due to the difficulty in creating ultra-shallow junctions and the incompatibility of thick silicon germanium layers with thin body devices.
Innovation Solution
A method involving the growth of a silicon germanium layer over a silicon layer on an insulating layer, followed by heating to condense germanium and form a silicon germanium channel under the gate stack, with a second silicon layer added and precise control over the germanium fraction and thickness to satisfy the relation X0·Ti=X·(Lg/2+Lsp), allowing for the formation of a thin and high-performance conduction channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a full sheet epitaxy of silicon germanium is formed on a silicon substrate, then a silicon germanium layer is produced, but the layer becomes too thick and is not compatible with thin body devices
Solution Approach 1:
The silicon germanium layer is segmented into two distinct parts: a thin silicon layer (first thickness) and a thicker silicon germanium layer (second thickness) formed above it. This segmentation allows the thin silicon portion to serve as the channel for thin body device compatibility, while the thicker SiGe layer provides the desired quantity without compromising device adaptability
Solution Approach 2:
The invention introduces a vertical dimensionality change by stacking the thin silicon layer beneath the thicker SiGe layer. This vertical arrangement enables the system to satisfy both thickness requirements in different spatial zones, resolving the contradiction between total SiGe quantity and thin body compatibility
2Reliability
If ultra-shallow junctions are formed in bulk silicon, then short channel effects are controlled, but the junction thickness becomes extremely thin (less than 10 nanometers) which is hard to achieve
Solution Approach 1:
The invention changes the material parameter from pure silicon to silicon germanium alloy, and adjusts the germanium concentration gradient through the layered structure. This parameter change enables effective short channel control with a more manufacturable junction thickness, avoiding the extreme precision requirements of ultra-thin silicon junctions
3Reliability
If thin silicon films on insulator are used in a fully depleted structure, then short channel effects are controlled, but the silicon film thickness must be less than 15 nm which limits device design flexibility
Solution Approach 1:
The invention applies local quality by creating a silicon germanium channel with spatially varying germanium concentration. The channel region has optimized composition for carrier mobility, while the layer structure above and below provides mechanical support and electrical isolation, enabling short channel control without restricting overall device design flexibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of a thin silicon germanium channel with improved mobility and precise control over short channel effects, allowing for better control of the insulating oxide layer and compatibility with various device architectures, including planar and FinFET architectures, while maintaining cost-effectiveness and scalability.
Implementation Method 1
heating the device so that germanium condenses in said silicon layer such that a silicon germanium channel is formed
Implementation Method 2
germanium condenses in said silicon layer such that a silicon germanium channel is formed
Data Source
AI summary
A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.