SiGe Channel MOSFET Structure for Higher Drive Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing MOSFET devices face challenges in increasing drive current, which is crucial for better device performance, due to limitations in channel mobility.
Innovation Solution
A semiconductor device is designed with a channel layer made of silicon germanium, which has a larger lattice constant than the substrate, thereby exerting a compressive force and increasing channel mobility. The device includes a gate structure with a dielectric layer and a work function metal layer, and conductive contacts made of specific materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicon channel layer is used in a MOSFET device, then the device structure is simple and manufacturing is easy, but the channel mobility is limited and drive current is low
Solution Approach 1:
The patent changes the material composition parameter of the channel layer from pure silicon to silicon germanium alloy, specifically controlling the germanium content to achieve the desired lattice mismatch. This parameter change enables the channel layer to exert compressive stress on the underlying silicon channel, thereby improving channel mobility and drive current while maintaining manufacturing feasibility through established epitaxial growth techniques
Solution Approach 2:
The patent employs a composite material structure where a silicon germanium channel layer is formed over a silicon substrate. The silicon germanium layer combines silicon and germanium elements to create a material with tailored lattice constant and mechanical properties. This composite approach allows the channel layer to provide compressive stress to enhance carrier mobility while remaining compatible with existing silicon-based semiconductor manufacturing processes
2Productivity
If the channel layer lattice constant is made larger than the substrate lattice constant, then channel mobility increases due to compressive force, but manufacturing precision requirements increase
Solution Approach 1:
The patent precisely controls the germanium concentration parameter in the silicon germanium channel layer to achieve a specific lattice constant that is slightly larger than the silicon substrate. By adjusting the germanium content within a controlled range, the patent optimizes the lattice mismatch to generate the desired compressive stress while staying within acceptable manufacturing tolerances for epitaxial growth processes
Solution Approach 2:
The patent applies the lattice mismatch effect locally at the interface between the silicon germanium channel layer and the silicon substrate. The compressive stress is generated specifically at this interface region, where the lattice constant difference creates mechanical stress that enhances carrier mobility in the channel region without requiring the entire device structure to meet stringent precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a silicon germanium channel layer with a larger lattice constant than the substrate increases channel mobility and drive current in MOSFET devices, enhancing overall device performance.
Implementation Method 1
the channel layer includes silicon germanium and is configured to exert a compressive force... the substrate has a different lattice constant from the channel layer
Implementation Method 2
exert a compressive force to the channel between source/drain regions... the channel layer... is configured to exert a compressive force
Data Source
AI summary
A semiconductor device includes a substrate, a channel layer, a source/drain region and a gate structure. The channel layer is located on the substrate, in which the channel layer includes silicon germanium. The source/drain region is adjacent to the channel layer. The gate structure is located on the channel layer, in which the gate structure includes a dielectric layer and a work function metal layer. The dielectric layer is located on the channel layer. The work function metal layer is located on the dielectric layer.