Silicon-Germanium Channel Gate Insulation Thermal Stability
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Solution Overview
Problem
Highly integrated semiconductor devices require advanced patterning technologies that increase manufacturing costs, and existing methods face challenges in forming reliable gate insulating layers on silicon-germanium channel layers without causing thermal instability and electrical characteristic deterioration.
Innovation Solution
A method involving the sequential formation of low-temperature and high-temperature insulating layers on a silicon-germanium channel layer, where the low-temperature layer is in contact with the channel layer and the high-temperature layer is formed at a higher temperature, reducing crystal defects and improving thermal stability, and the layers are strategically removed and reformed in specific regions to optimize transistor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a single high-temperature insulating layer is formed on the silicon-germanium channel layer, then the thermal stability is improved, but germanium atom escape and trap site formation increase causing electrical characteristic deterioration
Solution Approach 1:
The gate insulating layer is divided into two distinct layers: a first gate insulating layer formed at a lower temperature (below 750°C) and a second gate insulating layer formed at a higher temperature (above 750°C). This segmentation allows each layer to perform its function optimally without causing germanium atom escape, thereby resolving the contradiction between thermal stability and electrical characteristic reliability.
Solution Approach 2:
The formation temperature is changed as a critical parameter between the two gate insulating layers. The first layer is formed at a lower temperature to prevent germanium atom escape, while the second layer is formed at a higher temperature to provide thermal stability. This parameter change strategy enables both requirements to be satisfied simultaneously.
2Productivity
If advanced fine patterning technologies are used to manufacture highly integrated semiconductor devices, then the integration level is improved, but the manufacturing cost increases
Solution Approach 1:
By changing the formation temperature parameter to create a dual-layer gate insulating structure, the patent enables highly integrated semiconductor devices to be manufactured without requiring advanced fine patterning technologies. This approach maintains high integration levels while reducing manufacturing complexity and cost.
3Reliability
If the first gate insulating layer is formed at a lower temperature, then germanium atom escape is minimized, but the thermal stability is reduced
Solution Approach 1:
The gate insulating layer is segmented into two functional layers with different formation temperatures. The first layer at lower temperature preserves electrical characteristics by preventing germanium atom escape, while the second layer at higher temperature provides the necessary thermal stability, thus resolving the contradiction between reliability and thermal stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the deterioration of electrical characteristics and improves the thermal stability of semiconductor devices by minimizing germanium atom escape and trap site formation, leading to enhanced performance and reliability.
Implementation Method 1
forming a first insulating layer at a first temperature and a second insulating layer at a second temperature higher than the first temperature on the silicon-germanium channel layer
Implementation Method 2
forming a second insulating layer at a second temperature higher than the first temperature on the silicon-germanium channel layer
Data Source
AI summary
Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.