SiGe Cladding on FinFET Channels for High Mobility
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Solution Overview
Problem
The challenge in fabricating FinFETs lies in maintaining high mobility at smaller gate pitches due to reduced stress from source/drain SiGe stressors, limiting further improvements in channel mobility and scaling.
Innovation Solution
Incorporating a SiGe cladding layer onto the channel area of silicon fins, which can be enhanced with a SiGe source/drain stressor, and optionally capped with silicon to improve the gate dielectric/semiconductor interface, allowing for built-in stress and compatibility with existing process flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain SiGe stressors are used to improve channel mobility, then channel mobility is enhanced, but the stress decreases at smaller gate pitches, limiting further scaling
Solution Approach 1:
The patent transitions from planar stress application (source/drain stressors only) to three-dimensional stress application by cladding SiGe on the fin surfaces. This dimensional change allows stress to be applied from multiple directions (sidewalls and top surface), maintaining effective stress on the channel even as gate pitch decreases, thereby resolving the contradiction between improving mobility and scaling to smaller dimensions
Solution Approach 2:
The patent creates a composite structure by combining SiGe cladding layers with the silicon fin channel. This composite material approach allows the SiGe to provide built-in compressive stress to the silicon channel, enhancing carrier mobility while the overall structure can be scaled to smaller gate pitches without losing the stress effect
2Reliability
If SiGe cladding layer is added to provide built-in stress, then channel strain is enhanced, but device structure and fabrication process become more complex
Solution Approach 1:
The patent merges the stress application function into the fin structure fabrication process itself by depositing SiGe cladding layers during fin formation. This integration means that the complexity of adding stress is combined with the existing fin fabrication steps, rather than being a separate additional process, thereby reducing the overall impact on fabrication complexity while still achieving enhanced channel strain
Solution Approach 2:
The SiGe cladding layer provides self-service by automatically providing built-in compressive stress to the channel through its material properties and lattice mismatch with silicon. The stress is inherently generated by the cladding process itself, eliminating the need for separate stress application mechanisms or additional complex processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances channel strain, maintaining high mobility and enabling further scaling and performance improvements in FinFETs by providing compressive stress, particularly beneficial for PMOS devices.
Implementation Method 1
a cladding layer of germanium or silicon germanium (SiGe) on one or more surfaces of the channel region of the fin
Implementation Method 2
the built-in stress from a deposited SiGe cladding layer on a silicon fin can be enhanced with a SiGe source/drain stressor that compresses both the fin and SiGe cladding layers in the channel area
Data Source
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Figure 8a~8d
AI summary
Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the builtin stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric / semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric / semiconductor interface.