SiGe Capping Layer for CMOS Gate Electrode Formation
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Solution Overview
Problem
The varying dry and wet etch rates of p-type and n-type doped polysilicon layers make it difficult and inconsistent to form trenches for metal or silicide gate electrodes, leading to damage and performance degradation in CMOS devices.
Innovation Solution
A method involving a substrate with semiconducting multilayer features, including a dielectric layer and a silicon germanium capping layer, where the capping layer is selectively etched to form trenches, allowing for controlled etching of the polysilicon layer without damaging other features, and a low-temperature metal is deposited to form gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional polysilicon gates are used, then the process is simple and compatible with existing technology, but gate leakage currents are unacceptably high and device characteristics are significantly degraded
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or copper), which fundamentally alters the electrical properties and eliminates polysilicon depletion effects that cause high gate leakage currents in high-k dielectric structures
Solution Approach 2:
The gate electrode is segmented into multiple metal layers with different functions: a first metal layer provides gate functionality while a second metal layer (such as tungsten) provides structural support and stress control, allowing optimization of both electrical performance and mechanical stability
2Manufacturing precision
If p-type and n-type doped polysilicon layers are etched, then trenches can be formed for metal gate replacement, but the varying etch rates cause inconsistent trench depths and damage to spacer features
Solution Approach 1:
A silicon germanium (SiGe) capping layer is introduced as an intermediary sacrificial layer between the polysilicon layers and the metal gate. This layer has distinct etch selectivity, allowing it to be removed selectively to define trench depths without being affected by the varying etch rates of doped polysilicon, thereby eliminating overetch damage to spacers and ensuring consistent trench formation
Solution Approach 2:
The SiGe capping layer is deposited and patterned in advance before the metal gate formation process. This preliminary structure serves as a depth-stop mask that pre-defines the trench depth, allowing subsequent etching processes to proceed without risk of overetching, thus simplifying the overall manufacturing process while improving precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes damage and variation in etch depth, enabling more predictable metal gate replacement and fully silicided gate processes, reducing process bias and improving device performance.
Implementation Method 1
implanting at least one dopant into the features and the substrate surface, where an energy of the implant and a thickness of the SiGe layer are selected to limit a concentration of the dopant in the polysilicon layer to less than 10^18 atoms/cm3
Implementation Method 2
selectively etching the SiGe layer, where the etching removes the capping layer and at least a portion of the polysilicon layer
Implementation Method 3
depositing a low temperature metal on the dielectric layer to form gate electrodes for a plurality of MOS transistors in the integrated circuit
Data Source
AI summary
A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can also include forming spacers on sidewalls of the plurality of features, etching the capping layer, where the etching comprises selectively removing the capping layer, removing at least a portion of the base layer to form a plurality of trenches, and forming gate electrodes in the trenches.