SiGe Source/Drain Contacts With Gallium Segregation for Lower Resistance
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Solution Overview
Problem
As semiconductor technology scales down beyond 32 nm, source/drain contact resistance becomes a dominant factor in transistor resistance, and existing methods are inadequate in effectively reducing this resistance.
Innovation Solution
The method involves implanting gallium into source/drain features with a silicon germanium alloy, followed by specific annealing processes to recrystallize the alloy and segregate gallium atoms, thereby reducing contact resistance. This includes selecting a suitable Ge:Si ratio in the SiGe alloy to enhance gallium solubility and performing annealing at specific temperatures to repair defects and segregate gallium ions at the top of the features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contact formation methods are used in scaling beyond 32 nm, then manufacturing simplicity is maintained, but source/drain contact resistance becomes dominant and increases
Solution Approach 1:
The patent changes the material composition parameter by forming a silicon germanium alloy layer with specific Ge:Si ratios (e.g., 1:1 to 3:1) in the source/drain features. This compositional parameter change enhances gallium solubility and reduces contact resistance. Additionally, the annealing temperature parameter is optimized to specific ranges (525-575°C) to achieve defect repair and gallium segregation without forming harmful compounds.
Solution Approach 2:
The patent performs preliminary actions by first forming the silicon germanium alloy layer in the source/drain features before contact formation, and then performing a first annealing process to repair defects and segregate gallium ions to strategic positions. This preliminary preparation of the source/drain region creates optimal conditions for subsequent contact formation, reducing contact resistance before the actual contact is made.
2Reliability
If gallium is implanted into SiGe alloy without optimized Ge:Si ratio, then contact resistance reduction is attempted, but gallium solubility is insufficient and defects remain
Solution Approach 1:
The patent precisely controls the Ge:Si ratio parameter in the silicon germanium alloy, specifying ranges such as 1:1 to 3:1. This parameter optimization directly enhances gallium solubility in the alloy. The method also controls the annealing temperature parameter within specific ranges (525-575°C) to achieve optimal gallium segregation while preventing compound formation, demonstrating precise parameter management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces source/drain contact resistance by improving the conductivity of the SiGe alloy and preventing the formation of stable compounds that increase resistance, thereby enhancing the performance of p-type FinFETs.
Implementation Method 1
implanting gallium into source/drain features with a silicon germanium alloy
Implementation Method 2
performing specific annealing processes to recrystallize the alloy and segregate gallium atoms
Implementation Method 3
performing a first annealing process at a recrystallization temperature of the SiGe
Implementation Method 4
segregate gallium ions at the top of the features
Data Source
AI summary
A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.