Si/SiGe Epi Stack Strain Compensation for Reduced Wafer Bow
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Solution Overview
Problem
Heteroepitaxial semiconductor devices face strain-induced wafer bow due to lattice mismatch between silicon (Si) and silicon-germanium (SiGe) layers, which is more pronounced in thicker layers and complicates manufacturing, especially for dynamic random-access memory (DRAM) devices.
Innovation Solution
The method involves adding n-type dopants like phosphorous to the SiGe layer, using carbon and carbon-boron combinations to adjust etch rates, and incorporating tensile silicon layers to compensate for strain and reduce wafer bow, either during or after the growth process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heteroepitaxial growth of Si/SiGe films is performed, then semiconductor device functionality is achieved, but strain-induced wafer bow occurs due to lattice mismatch
Solution Approach 1:
The patent segments the SiGe layer into multiple thinner sub-layers separated by Si spacer layers. This segmentation reduces the cumulative strain in each individual SiGe layer, thereby minimizing wafer bow while preserving the overall device functionality that requires SiGe structures.
Solution Approach 2:
The patent modifies the thickness parameter of SiGe layers, using thinner layers compared to conventional approaches. By reducing the thickness of individual SiGe layers and introducing Si spacer layers, the strain accumulation is controlled, achieving wafer bow reduction while maintaining device performance.
2Reliability
If thicker SiGe layers are used, then device performance is improved, but wafer bow becomes unmanageable
Solution Approach 1:
Instead of using a single thick SiGe layer that causes excessive wafer bow, the patent divides the desired SiGe functionality into multiple thinner layers. This segmentation allows achieving the required device performance through cumulative effect of multiple layers while keeping individual layer thickness below the bow-inducing threshold.
Solution Approach 2:
The patent introduces Si spacer layers as intermediary elements between SiGe layers. These spacer layers act as stress-relief mediators, preventing strain accumulation between adjacent SiGe layers and enabling the use of thicker overall SiGe structures without excessive wafer bow.
3Reliability
If Si/SiGe heteroepitaxial structure is formed, then lattice mismatch strain is introduced, but crystal defects are prevented through controlled growth
Solution Approach 1:
The patent segments the SiGe structure into thinner layers with Si spacers, which distributes and reduces the lattice mismatch strain in each interface. This segmentation maintains crystal quality by preventing strain-induced defects while still achieving the desired heteroepitaxial structure functionality.
Solution Approach 2:
The patent optimizes the thickness parameters of SiGe layers and Si spacer layers to control strain levels. By carefully selecting layer thicknesses, the patent maintains crystal quality and prevents defects while managing the inherent lattice mismatch strain in Si/SiGe heteroepitaxial growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces wafer bow and strain, enhances selective etching, and prevents crystal defects, improving the manufacturing process for semiconductor devices by compensating for lattice mismatch and adjusting layer thicknesses and doping concentrations.
Implementation Method 1
capable of reducing strain that may be induced by a mismatch in lattice elements
Implementation Method 2
a strain may be introduced from a mismatch in lattice elements of Si lattice and Ge lattice
Implementation Method 3
forming at least one tensile layer on a bottom of at least one silicon layer
Implementation Method 4
A wafer bow may be produced as result
Implementation Method 5
forming at least one p-type stop layer on top of the n-type doped silicon layer
Data Source
AI summary
A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.