SiGe Epitaxial Layer for Integrated BiCMOS Transistors
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Solution Overview
Problem
The complex fabrication process of integrated BiCMOS circuits, which require multiple epitaxial layers for both bipolar and CMOS transistors, necessitates a simplification to reduce the number of process steps while leveraging the benefits of silicon-germanium for improved transistor performance.
Innovation Solution
A method involving the epitaxial growth of a silicon-germanium epitaxial layer with two different germanium concentrations and dopant profiles, allowing for the simultaneous formation of base regions for bipolar transistors and channel regions for CMOS transistors, reducing the number of necessary process steps and enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If four different epitaxial layers are formed to provide SiGe for both bipolar and CMOS transistors, then transistor performance is improved, but fabrication process complexity increases
Solution Approach 1:
The patent combines the formation of base regions for bipolar transistors and channel regions for CMOS transistors into a single epitaxial layer. This single layer contains SiGe at multiple depth positions, simultaneously serving as the base for NPN/PNP bipolar transistors and the channel for NMOS/PMOS transistors, thereby reducing the number of epitaxial layers from four to one and simplifying the fabrication process.
Solution Approach 2:
The epitaxial layer is designed with spatially varying SiGe concentration and dopant distribution. By controlling the depth-dependent composition, the same layer provides different local properties: SiGe near the surface for CMOS channel mobility enhancement and SiGe at deeper positions for bipolar base performance, achieving localized functionality within a unified structure.
2Reliability
If multiple epitaxial layers are formed with different SiGe depths, then both bipolar and CMOS transistors achieve high performance, but the number of process steps increases
Solution Approach 1:
The patent merges multiple epitaxial growth steps into a single continuous epitaxial process. By growing one epitaxial layer with controlled SiGe incorporation at different depths during the growth process, the method eliminates the need for separate growth, masking, and deposition steps for each layer, significantly reducing the total number of fabrication process steps.
Solution Approach 2:
The SiGe distribution and dopant profiles are predetermined during the single epitaxial growth process. The growth conditions are carefully controlled to pre-establish the required SiGe concentration gradients and dopant distributions that will subsequently serve both bipolar and CMOS devices, eliminating the need for later corrective or additional doping steps.
3Device complexity
If SiGe is added at multiple depths in a single epitaxial layer, then the fabrication process is simplified, but precise control of SiGe concentration and dopant distribution is required
Solution Approach 1:
The patent utilizes dynamic parameter changes during the epitaxial growth process. By varying the SiGe source flow rate, temperature, and pressure conditions at different stages of the growth, the method achieves precise control over SiGe concentration and dopant distribution at multiple depths within the single epitaxial layer, overcoming the precision challenge through process parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process by forming multiple epitaxial layers in fewer steps, improving the performance of both bipolar and CMOS transistors through strained lattice structures and retrograde dopant profiles, thereby increasing transit time reduction and carrier mobility.
Implementation Method 1
The step of forming the epitaxial layer includes epitaxially growing a first sublayer of silicon; epitaxially growing a first sublayer of silicon-germanium onto the first sublayer of silicon; epitaxially growing a second sublayer of silicon onto the first sublayer of silicon-germanium; and epitaxially growing a second sublayer of silicon-germanium onto the second sublayer of silicon
Implementation Method 2
epitaxially growing a first sublayer of silicon-germanium onto the first sublayer of silicon; epitaxially growing a second sublayer of silicon-germanium onto the second sublayer of silicon. Germanium is added twice to the epitaxial layer, thus forming an epitaxial layer with silicon-germanium in two different depths
Implementation Method 3
the first sublayer of silicon-germanium is increasingly doped in situ with a dopant, and the second sublayer of silicon is decreasingly doped in situ with the dopant
Data Source
AI summary
A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.