SiGe Epitaxial Growth Selectivity and Morphology Control

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Solution Overview

Problem

Existing semiconductor device fabrication methods face challenges in achieving selective growth of SiGe or SiC layers at low temperatures without morphological deterioration, which affects the electrical characteristics of recessed source/drain MOSFETs, particularly due to the trade-off between growth selectivity and morphology.

Innovation Solution

A method involving the formation of a semiconductor device with a gate electrode and insulating layers, where a second semiconductor layer is grown in recesses with a lower layer portion and an upper layer portion, controlling growth selectivity by varying the halogen gas content and temperature to suppress morphological deterioration and ensure selective growth over insulating layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If halogen gas content is increased to improve growth selectivity of SiGe layer over insulating layers, then growth selectivity is improved, but morphology deteriorates with partial delay in SiGe layer growth

Engineering Contradiction:
Improvegrowth selectivityVSAvoidmorphology
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The patent applies dynamics by making the growth conditions variable rather than static. Specifically, the growth temperature and halogen gas content are dynamically adjusted during the epitaxial growth process - starting at lower temperatures with lower halogen content to ensure good morphology, then increasing temperature and halogen content to achieve high growth selectivity. This temporal variation in growth parameters resolves the contradiction between morphology and selectivity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action through multi-stage epitaxial growth with distinct phases. The process is divided into multiple periods: an initial growth period with controlled halogen content and temperature for morphology formation, followed by subsequent periods with increased halogen content for selective growth. This periodic adjustment of growth conditions allows both morphology and selectivity requirements to be met at different stages.

Inventive Principle:
Principle #19Periodic action

2Manufacturing precision

If SiGe layer is grown at high temperature to achieve selective growth, then growth selectivity is improved, but misfit dislocations appear and stress weakens

Engineering Contradiction:
Improvegrowth selectivityVSAvoidstress in channel region
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent uses dynamic temperature control during epitaxial growth. Instead of maintaining a constantly high temperature, the process starts at lower temperatures to preserve lattice matching and stress, then dynamically increases temperature to achieve selective growth. This temporal temperature variation allows the system to benefit from both low-temperature stress preservation and high-temperature selective growth.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies parameter changes by systematically varying multiple growth parameters including temperature, halogen gas content, and pressure throughout the epitaxial process. By changing these parameters in a coordinated manner - initially using lower temperatures and gradually increasing them - the patent achieves selective growth while maintaining adequate stress in the channel region.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If SiGe layer is grown at high temperature, then growth rate is improved, but impurity diffusion occurs and device characteristics deteriorate

Engineering Contradiction:
Improvegrowth rateVSAvoiddevice characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements periodic action through staged growth periods with different temperature regimes. The process includes an initial period at lower temperatures where growth rate is sacrificed to prevent impurity diffusion, followed by subsequent periods at higher temperatures where growth rate is enhanced. This periodic temperature adjustment allows both low-diffusion and high-productivity requirements to be met at different stages.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies preliminary action by performing low-temperature growth first to establish a foundation layer with minimal impurity diffusion, before proceeding to high-temperature growth. This preliminary low-temperature stage prepares the structure in advance, preventing subsequent impurity contamination while allowing faster growth later.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the stable fabrication of semiconductor devices with improved electrical characteristics by controlling growth selectivity and morphology, enhancing the performance of recessed source/drain MOSFETs by maintaining high selectivity and preventing morphological deterioration.

Implementation Method 1

forming a second semiconductor layer having a lower layer portion and an upper layer portion in the recesses, the lower layer portion and the upper layer portion being made to grow under a condition that growth selectivity of the lower layer portion with respect to the insulating layer is lower than growth selectivity of the upper layer portion with respect to the insulating layer

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

a method in which Si material gas, germanium (Ge) material gas, and the like and halogen gas, such as hydrogen chloride (HCl) gas, are added

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS8293622B2Semiconductor device fabrication method, semiconductor device, and semiconductor layer formation method
Publication Date: 2012.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8293622B2 patent drawing
  • US8293622B2 patent drawing
  • US8293622B2 patent drawing

AI summary

A semiconductor device fabrication method and a semiconductor layer formation method for making a semiconductor layer having excellent morphology selectively epitaxial-grow over a semiconductor, and a semiconductor device. When a recessed source/drain pMOSFET is fabricated, a gate electrode is formed over a Si substrate in which STIs are formed with a gate insulating film therebetween (step S1). After a side wall is formed (step S2), recesses are formed in portions of the Si substrate on both sides of the side wall (step S3). A SiGe layer including a lower layer portion and an upper layer portion is formed in the recesses of the Si substrate. The lower layer portion and the upper layer portion included in the SiGe layer are made to epitaxial-grow under a condition that growth selectivity of the lower layer portion with respect to the side wall and the STIs is lower than growth selectivity of the upper layer portion with respect to the side wall and the STIs (steps S4 and S5). As a result, the SiGe layer the growth selectivity of which with respect to the side wall and the like is secured and in which morphological deterioration is suppressed can be formed in the recesses of the Si substrate.