SiGe Epitaxial Layering for Low-Defect Multi-Gate Source/Drain
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Solution Overview
Problem
Conventional epitaxial features in multi-gate transistors, such as MBC transistors, face challenges with increased germanium content in source/drain features leading to interface defects and higher contact resistance, while higher doping concentrations also result in defects, limiting the reduction of resistance and strain on channel members.
Innovation Solution
The semiconductor device incorporates a first epitaxial layer to interface with channel members, minimizing its volume to maximize the second epitaxial layer's volume, which has a higher germanium content and doping concentration to reduce resistance and enhance strain, while the third epitaxial layer serves as a sacrificial layer for source/drain contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If germanium content in source/drain features is increased to reduce resistance and enhance strain on channel members, then resistance is reduced and strain is enhanced, but interface defects increase and contact resistance increases
Solution Approach 1:
The source/drain feature is segmented into multiple epitaxial layers with different germanium contents. The first epitaxial layer has lower germanium content (20-40%) to interface with channel members and minimize defects, while the second epitaxial layer has higher germanium content (40-60%) to provide strain and reduce resistance. This segmentation allows each layer to optimize for its specific function without compromising the other.
Solution Approach 2:
Different regions of the source/drain feature are assigned different material compositions tailored to local requirements. The region interfacing with channel members uses lower germanium content to ensure quality interfaces, while the region providing strain and conduction paths uses higher germanium content. This local quality differentiation resolves the contradiction between reducing defects and enhancing performance.
2Reliability
If doping concentration in source/drain features is increased to reduce resistance, then resistance is reduced, but defects increase
Solution Approach 1:
The doped epitaxial layer is segmented into multiple sub-layers with progressively increasing doping concentrations. The first doped layer has lower doping concentration to minimize defects at the interface with channel members, while subsequent doped layers have higher doping concentrations to reduce resistance. This gradual transition reduces defect formation while achieving the desired electrical conductivity.
Solution Approach 2:
The doping concentration parameter is varied across different epitaxial layers rather than being uniform. By changing the doping concentration parameter from layer to layer, the patent achieves low resistance in high-doping regions while maintaining low defect densities in regions interfacing with channel members.
3Reliability
If volume of first epitaxial layer is minimized to maximize second epitaxial layer volume, then resistance is reduced and strain is enhanced, but interface quality may be compromised
Solution Approach 1:
The first epitaxial layer is designed with locally optimized thickness - thin enough to allow strain transmission and electrical conduction, but sufficient to provide a quality interface. The layer thickness is precisely controlled to balance these competing requirements, ensuring both interface quality and effective strain/R resistance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic resistance in the source/drain features, improving the strain on channel members and lowering contact resistance, thereby enhancing the performance of multi-gate transistors.
Implementation Method 1
depositing a first epitaxial layer in the source/drain trench, the first epitaxial layer being in contact with the plurality of silicon layers
Implementation Method 2
a second epitaxial layer over the first epitaxial layer, the second epitaxial layer being in contact with the plurality of inner spacer features and the first epitaxial layer
Data Source
AI summary
The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.