SiGe Source/Drain Epitaxy With Graded Doping for Short-Channel Control
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Solution Overview
Problem
The existing method of manufacturing semiconductor devices using a silicon-germanium (SiGe) layer to enhance carrier mobility in PMOSFETs faces challenges where the addition of impurities like boron leads to diffusion during heat treatment, causing the short channel effect, which can be mitigated by increasing the distance between the SiGe layer and the channel region, but this reduces stress and carrier mobility.
Innovation Solution
A method involving the epitaxial growth of a mixed crystal layer with a concentration gradient of impurities, where the impurity concentration increases from the silicon substrate towards the surface, allowing for lower impurity diffusion and maintaining sufficient carrier mobility without the need to enlarge the distance between the SiGe layer and the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If impurity such as boron is added to the SiGe layer to form source/drain regions, then the source/drain regions are formed effectively, but the impurity diffuses during heat treatment causing the short channel effect
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the SiGe layer. The first SiGe layer has a first impurity concentration while the second SiGe layer has a second impurity concentration, allowing localized control of impurity distribution to prevent diffusion while maintaining manufacturing effectiveness.
Solution Approach 2:
The SiGe layer is segmented into multiple layers with different impurity concentrations. This segmentation allows the impurity distribution to be controlled locally, preventing the short channel effect while maintaining effective source/drain region formation during heat treatment.
2Reliability
If the distance between the SiGe layer and the channel region is enlarged to prevent impurity diffusion, then the short channel effect is mitigated, but the stress on the channel region is reduced and carrier mobility decreases
Solution Approach 1:
The patent uses local quality by implementing a graded impurity concentration profile across the SiGe layer thickness. This allows the SiGe layer to remain close to the channel region for effective stress application while the impurity concentration gradient prevents excessive diffusion into the channel, maintaining both reliability and carrier mobility.
3Speed
If the SiGe layer is placed closer to the channel region to increase stress and carrier mobility, then transistor performance is enhanced, but impurity diffusion during heat treatment increases causing the short channel effect
Solution Approach 1:
The patent resolves this contradiction by applying local quality through a vertically graded impurity concentration profile in the SiGe layer. The impurity concentration varies through the thickness of the SiGe layer, allowing the layer to be positioned close to the channel for effective stress application while preventing impurity diffusion into the channel region during heat treatment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the short channel effect while ensuring sufficient carrier mobility and transistor performance, enhancing the manufacturing process by restraining impurity diffusion and maintaining stress on the channel region.
Implementation Method 1
a mixed crystal layer including silicon and atoms different in lattice constant from silicon is epitaxially grown on the surface of the dug-down portion of the silicon substrate
Implementation Method 2
the impurity in the SiGe layer would be diffused (diffused regions A) by the heat treating or heating steps carried out in the subsequent steps
Data Source
AI summary
A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.