SiGe Source/Drain Epitaxy Profile Control at Isolation Interfaces
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Solution Overview
Problem
The formation of faceted profiles in silicon germanium epitaxial layers on source/drain terminals of fin field effect transistors due to lattice mismatch between crystalline and amorphous surfaces, leading to non-uniform thickness and challenging contact formation.
Innovation Solution
Formation of a silicon germanium nanostructure at the interface of the semiconductor/isolation region to promote uniform growth of SiGe epitaxial layers with a horizontal top surface, using Ge implantation and thermal annealing to create a lattice-matched growth surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon germanium epitaxial layers are grown on source/drain terminals between active semiconductor region and dielectric isolation region, then the epitaxial layers can be formed, but they develop a faceted profile due to lattice mismatch between crystalline and amorphous surfaces
Solution Approach 1:
A silicon germanium nanostructure is formed at the interface of the semiconductor/isolation region before growing the epitaxial layer. This preliminary structure serves as a lattice-matched template that guides the subsequent epitaxial growth, preventing facet formation and ensuring uniform thickness from the start.
Solution Approach 2:
The silicon germanium nanostructure acts as an intermediary layer between the amorphous dielectric isolation region and the crystalline epitaxial layer. It provides a crystalline interface that matches the lattice structure of the incoming epitaxial material, eliminating the lattice mismatch problem at the interface.
2Productivity
If silicon germanium epitaxial layers are grown directly on the isolation region interface, then growth can proceed, but the thickness becomes non-uniform due to faceting
Solution Approach 1:
The silicon germanium nanostructure is formed in advance at the growth interface, creating a prepared surface that promotes uniform epitaxial growth. This preliminary structure ensures that the epitaxial layer grows uniformly from the interface without developing facets that would cause thickness variations.
3Manufacturing precision
If a silicon germanium nanostructure is formed at the semiconductor/isolation region interface, then uniform epitaxial layer growth is achieved, but additional process steps are required
Solution Approach 1:
The formation of the silicon germanium nanostructure involves changing local compositional parameters (introducing germanium) at the interface region. This parameter change creates the lattice-matched structure needed for uniform growth, and the germanium can be introduced through standard ion implantation processes already used in semiconductor fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures uniform thickness and horizontal top surfaces of SiGe epitaxial layers, improving the etching process window for contact openings and reducing the risk of electrical shorts and non-uniform etching.
Implementation Method 1
using Ge implantation and thermal annealing to create a lattice-matched growth surface
Implementation Method 2
using Ge implantation and thermal annealing to create a lattice-matched growth surface
Implementation Method 3
Silicon germanium epitaxial layers formed on source/drain terminals of a fin field effect transistor (FINFET) or a planar FET
Data Source
AI summary
The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.