SiGe Nanostructure Etching for Uniform Nanosheet Gate Regions
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Solution Overview
Problem
The etching of SiGe nanostructures in semiconductor devices leads to non-uniform gate regions, causing device performance and reliability issues due to Si nanosheet/nanowire channel loss, high surface roughness, and critical dimension non-uniformities, particularly between top and bottom SiGe nanostructures and fin structures with varying spacings.
Innovation Solution
A method involving native oxide removal, HF purge, and controlled F2/HF etching at low temperature and pressure, with specific gas ratios and multiple etching cycles to achieve uniformity, is employed to form uniform gate regions by reducing etching and critical dimension non-uniformities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching methods are used on SiGe nanostructures, then etching speed is achieved, but non-uniform gate regions and critical dimension non-uniformities occur
Solution Approach 1:
The etching process is divided into multiple sequential steps with different gas compositions and parameters. The method uses a multi-step etching sequence including CF4-based etching followed by F2-based etching, with intermediate HF purges, allowing each step to contribute differently to the overall etching while maintaining uniformity
Solution Approach 2:
The etching process employs periodic alternation between etching steps and HF purge steps. The HF purges are performed at intervals during the etching sequence to remove accumulated byproducts and reset the surface conditions, creating a periodic cycle that maintains consistent etching rates and uniformity across the nanostructures
2Productivity
If high temperature etching is used, then etching rate increases, but Si nanosheet/nanowire channel loss occurs
Solution Approach 1:
The method systematically varies multiple process parameters including temperature (maintained at lower ranges), pressure (reduced to 10-100 mTorr), gas flow rates, and gas composition ratios (F2:CF4 between 0.1-10). These parameter changes create optimal conditions for selective etching of SiGe while protecting Si nanosheets and nanowires from loss
3Productivity
If conventional etching is performed, then etching is completed, but high surface roughness and critical dimension non-uniformities result
Solution Approach 1:
Hydrogen fluoride (HF) is introduced as an intermediary substance that mediates between the etching process and the nanostructure surface. The HF purges act as intermediate steps that clean the surface of etching byproducts and prevent accumulation that would lead to roughness and non-uniformity, without causing significant material removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in substantially uniform gate regions, enhancing device performance and reliability by minimizing voids and improving surface roughness and spacer uniformity.
Implementation Method 1
purging the fin structure with hydrogen fluoride (HF)
Implementation Method 2
etching the end of the one or more nanostructures with a gas mixture of fluorine (F2) and HF
Data Source
AI summary
The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.