Silicon Germanium Fin Formation by Germanium Diffusion Annealing
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Solution Overview
Problem
The challenge in manufacturing FinFET devices lies in forming silicon germanium fins without etching the silicon substrate, which often results in epitaxial defects due to hetero-epitaxial growth, and existing methods are not cost-effective for large-scale production.
Innovation Solution
A method involving depositing a germanium layer over a silicon substrate, forming an oxide capping layer, and performing thermal annealing to diffuse germanium atoms into the substrate, creating a uniform silicon germanium layer without etching, thereby preventing defects and enabling mass production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hetero-epitaxial growth is used to form silicon germanium fins, then silicon germanium fins can be formed, but epitaxial defects such as kinks occur at corners
Solution Approach 1:
The patent changes the fundamental formation parameter from hetero-epitaxial growth to thermal diffusion process. By depositing a germanium layer and performing thermal annealing at temperatures between 700-900°C, germanium atoms diffuse into the silicon substrate to form silicon germanium fins. This parameter change eliminates the interface mismatch issues inherent in hetero-epitaxial growth, preventing kink defects at corners and achieving uniform silicon germanium distribution without epitaxial defects.
Solution Approach 2:
The patent replaces the mechanical/chemical deposition process of hetero-epitaxial growth with a thermal diffusion mechanism. Instead of growing silicon germanium layers through controlled deposition, the method uses thermal energy to drive germanium atom diffusion from the deposited germanium layer into the silicon substrate. This substitution of formation mechanism eliminates the stress and interface issues that cause kink defects in corner regions during epitaxial growth.
2Ease of manufacture
If existing methods are used for manufacturing silicon germanium fins, then fins can be formed, but the process is not cost-effective for large-scale production
Solution Approach 1:
The patent segments the manufacturing process into distinct, independently optimized steps: germanium layer deposition followed by thermal annealing. This segmentation allows each step to be performed using standard, well-established semiconductor fabrication equipment and processes, improving both cost-effectiveness and scalability for mass production compared to complex hetero-epitaxial growth methods.
Solution Approach 2:
The thermal annealing process is self-regulating, where germanium atoms automatically diffuse into the silicon substrate based on concentration gradients and thermal energy. This self-service mechanism reduces the need for complex process control and intervention, simplifying manufacturing and reducing costs for large-scale production while maintaining consistent quality across multiple wafers.
3Manufacturing precision
If germanium layer is annealed to diffuse germanium atoms into silicon substrate, then uniform silicon germanium is formed without defects, but the process requires precise temperature control
Solution Approach 1:
The patent establishes specific temperature ranges (700-900°C) and time parameters for the thermal annealing process that optimize germanium diffusion. By defining these parameter windows, the method achieves uniform germanium distribution in the silicon substrate while maintaining compatibility with standard semiconductor fabrication equipment capabilities, balancing precision requirements with practical process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents kinks and defects, allows for simultaneous fabrication on multiple wafers, and results in more uniform silicon germanium, enhancing the quality and reducing fabrication costs, while being compatible with FinFET device manufacturing.
Implementation Method 1
annealing the germanium layer to diffuse germanium atoms of the germanium layer into the silicon substrate
Implementation Method 2
forming an oxide capping layer over the germanium layer; after forming the oxide capping layer, annealing the germanium layer
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes depositing a germanium layer over a silicon substrate; forming an oxide capping layer over the germanium layer; after forming the oxide capping layer, annealing the germanium layer to diffuse germanium atoms of the germanium layer into the silicon substrate, such that a portion of the silicon substrate is turned into a silicon germanium layer; and forming a gate structure over the silicon germanium layer.