Defect-Free SiGe FinFET Formation via Germanium Diffusion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of alternative semiconductor materials like SiGe on silicon substrates is hindered by lattice mismatch, leading to unacceptable defects and the inability to form highly-strained, substantially defect-free silicon-germanium fins for FinFET devices, which affects device performance and reliability.
Innovation Solution
The method involves forming trenches in a silicon substrate, depositing a recessed layer of insulating material, and performing an epitaxial deposition of silicon-germanium followed by thermal annealing or oxidation to diffuse germanium into the fin, thereby creating a substantially defect-free silicon-germanium region, and then removing the excess material to form a gate structure around the silicon-germanium region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternative semiconductor materials like SiGe are integrated on silicon substrates, then device performance can be improved through strain enhancement, but lattice mismatch leads to unacceptable defects
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial SiGe layer and insulating material structure before final fin formation. The SiGe is deposited and annealed to diffuse germanium into the fin, then the sacrificial material is removed, leaving a defect-free SiGe fin. This preliminary preparation of the SiGe structure enables subsequent defect-free fin formation.
Solution Approach 2:
The patent uses an insulating material layer as an intermediary to control the SiGe diffusion process. The insulating material is recessed to expose the fin, allowing controlled diffusion of germanium from the SiGe layer into the silicon fin during thermal annealing. This intermediary structure enables precise control over where SiGe is incorporated, preventing defect formation at interfaces.
2Reliability
If highly-strained SiGe fins are formed directly through epitaxial growth, then strain can be introduced to improve carrier mobility, but lattice mismatch causes threading dislocations and defects
Solution Approach 1:
The patent performs preliminary thermal annealing to diffuse germanium from the deposited SiGe layer into the silicon fin before final fin structure completion. This preliminary diffusion process introduces strain gradually and uniformly, avoiding the sudden lattice mismatch that would cause threading dislocations during direct epitaxial growth.
Solution Approach 2:
The patent changes the physical and chemical parameters during processing by using thermal annealing at controlled temperatures to diffuse germanium atoms into the silicon lattice. This parameter control (temperature, time, atmosphere) enables precise control over SiGe concentration gradients, maintaining strain while avoiding defect formation that would occur with direct high-concentration epitaxial growth.
3Reliability
If the concentration of germanium in the epi silicon-germanium layer is made equal to or greater than the target concentration, then the final fin can achieve desired strain levels, but excess germanium may cause defects during diffusion
Solution Approach 1:
The patent uses parameter changes by controlling the thermal annealing temperature and duration to manage germanium diffusion. By optimizing these parameters, the process achieves complete germanium transfer from the SiGe layer to the fin without creating defects, even when the initial SiGe layer has germanium concentration equal to or greater than the target concentration. The controlled diffusion gradient prevents sudden lattice mismatch.
Solution Approach 2:
The insulating material layer serves as an intermediary that controls the diffusion interface. By recessing this layer to expose the fin surface, the patent creates a controlled interface where germanium diffusion occurs uniformly. This intermediary structure prevents the formation of defects that would arise from uncontrolled direct contact between high-concentration SiGe and the fin structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of fully-strained, substantially defect-free silicon-germanium fins, improving device performance by reducing defects and enhancing the operational reliability of FinFETs while being compatible with existing manufacturing processes.
Implementation Method 1
performing an epitaxial deposition process to form a layer of epi silicon-germanium (SixGe1-x) above the recessed layer of insulating material and on the exposed portion of the fin
Implementation Method 2
performing a thermal anneal process in an inert processing environment to cause germanium in the layer of epi silicon-germanium (SixGe1-x) to diffuse into the fin
Implementation Method 3
performing an oxidation process to convert at least a portion of the layer of epi silicon-germanium (SixGe1-x) into an oxide and to cause germanium in the layer of epi silicon-germanium (SixGe1-x) to diffuse into the fin
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.