SiGe Fin Gate Stack Design for CMOS Interface Trap Reduction
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Solution Overview
Problem
Conventional gate stack designs for silicon (Si) and silicon germanium (SiGe) dual channel devices suffer from performance degradation due to high interface trap density attributed to germanium oxide (GeOx) formation and germanium pile-up, which affects the performance of SiGe p-FETs in CMOS technology.
Innovation Solution
A method involving the formation of a Si-rich layer on SiGe fins through a reaction between silicon germanium oxide (SiGeOx) and SiGe, followed by annealing, which results in a low interface trap charge and high hole mobility, while maintaining the Si fin surface unchanged, thereby improving both analog and logic device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate stack designs are used for Si/SiGe dual channel devices, then device fabrication is straightforward, but interface trap density increases due to GeOx formation and Ge pile-up, degrading SiGe p-FET performance
Solution Approach 1:
A silicon-rich layer is formed on the SiGe fin surface before gate stack fabrication to prevent germanium oxide formation and germanium pile-up during subsequent processing steps. This preliminary protective layer eliminates interface trap density issues while maintaining conventional fabrication simplicity.
Solution Approach 2:
An intermediary silicon-rich layer is introduced between the SiGe fin and the gate stack. This intermediate layer acts as a barrier that prevents harmful interactions (GeOx formation and Ge pile-up) while allowing the device to be fabricated using standard processes.
2Reliability
If techniques to reduce interface trap density are applied to SiGe fins, then SiGe p-FET performance improves, but the process complexity increases
Solution Approach 1:
The silicon-rich layer formation process serves multiple functions simultaneously: it reduces interface trap density, prevents GeOx formation, prevents Ge pile-up, and maintains compatibility with conventional CMOS fabrication. This multi-functionality avoids increasing overall process complexity despite the added benefit.
3Reliability
If the SiGe surface is modified to reduce interface traps, then hole mobility increases, but the Si fin surface may be affected
Solution Approach 1:
The silicon-rich layer is selectively formed only on the SiGe fin surfaces, leaving the Si fin surfaces unchanged. This localized modification improves hole mobility in SiGe p-FETs while maintaining the original composition and properties of Si n-FETs, achieving device-specific optimization without cross-contamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces interface trap charges and enhances hole mobility in SiGe p-FETs, leading to improved performance of Si/SiGe dual channel CMOS devices by modifying only the SiGe surface without affecting the Si fin surface, thus addressing the performance degradation issues.
Implementation Method 1
annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe
Implementation Method 2
a reaction between SiGeOx and SiGe
Data Source
AI summary
Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.