SiGe P-Channel Fin Height and STI Depth Matching in FinFETs
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Solution Overview
Problem
Traditional FinFET devices face performance limitations due to tight gate dimensions and challenges in doping and strain engineering, especially at advanced process nodes like 5 nm and 3 nm, necessitating improvements in manufacturing processes for high-performance and low-power ICs.
Innovation Solution
The method involves forming p-channel and n-channel fins on a common substrate, using silicon germanium alloy for p-channel fins to enhance mobility, and employing iterative etching processes to achieve closely matched critical dimensions and fin heights, ensuring flatness of the isolation structure for improved gate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional FinFET devices are used with tight gate dimensions, then device scaling is achieved, but doping and strain engineering become very challenging
Solution Approach 1:
The patent changes the material parameter by introducing high-mobility semiconductor materials (such as SiGe, GaAs, InGaAs) to replace traditional silicon in FinFET channels. This material substitution enables improved carrier mobility without requiring further reduction in gate dimensions, thereby avoiding the manufacturing challenges associated with tight scaling while maintaining or enhancing device performance
Solution Approach 2:
The patent employs composite material structures where high-mobility semiconductor materials are integrated with silicon-based substrates and surrounding structures. This composite approach allows the device to benefit from the high mobility properties of advanced materials while maintaining compatibility with existing silicon fabrication processes, thus resolving the contradiction between scaling and manufacturability
2Productivity
If FinFET devices are downscaled to 5 nm and 3 nm process nodes, then device density increases, but performance limitations are approached
Solution Approach 1:
The patent changes the fundamental material parameter by adopting high-mobility semiconductor materials for the FinFET channel region. This material transition provides enhanced carrier mobility that compensates for the performance degradation typically observed at ultra-scaled nodes, allowing devices to maintain high performance while achieving increased density through continued downscaling
3Reliability
If p-channel fins use silicon germanium alloy, then mobility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by introducing silicon germanium alloy specifically in the p-channel fin regions where high hole mobility is required, while maintaining standard silicon in other device regions. This localized material modification targets the specific performance bottleneck in p-channel devices without requiring complex manufacturing changes across the entire device structure, thus enhancing mobility while controlling manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of p-type FinFETs by utilizing higher mobility materials and optimizes etching processes, resulting in improved flatness and manufacturability, thereby supporting advanced semiconductor device fabrication.
Implementation Method 1
the second semiconductor material is different from the first semiconductor material and has a higher charge carrier mobility than the first semiconductor material
Implementation Method 2
epitaxially growing a second semiconductor material in the trench
Data Source
AI summary
A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.