Silicon Germanium Fin Structure Without Epitaxial Kink Defects

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Solution Overview

Problem

The challenge in semiconductor manufacturing lies in forming high-performance silicon germanium fins for FinFET devices without introducing epitaxial defects, particularly kinks at corners, which are caused by etching the silicon substrate and hetero-epitaxial growth processes.

Innovation Solution

A method is developed to diffuse germanium atoms into a silicon substrate using a thermal treatment, forming a silicon germanium fin without etching the silicon substrate, thereby preventing defects and achieving uniform germanium distribution, which is more compatible with FinFET device fabrication and cost-effective for multiple wafer processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If etching the silicon substrate and hetero-epitaxial growth processes are used to form silicon germanium fins, then the fins can be created, but epitaxial defects such as kinks at corners are introduced

Engineering Contradiction:
Improvefin qualityVSAvoiddefect-free structure
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent extracts and eliminates the harmful etching and hetero-epitaxial growth steps from the fabrication process. By using selective germanium diffusion directly into the silicon substrate instead of these traditional steps, the method removes the root causes of kink defects and other epitaxial issues, achieving defect-free silicon germanium fin structures

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/chemical etching process and hetero-epitaxial growth with a thermal diffusion process. This substitution uses controlled thermal energy to diffuse germanium atoms into the silicon substrate, forming silicon germanium fins without the mechanical damage and defects associated with etching and epitaxial growth

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If conventional FinFET fabrication processes are used, then devices can be manufactured, but fabrication costs increase and process complexity increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidfabrication cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent changes the fundamental process parameters by replacing etching and epitaxial growth with thermal diffusion. This parameter change simplifies the fabrication process, reduces the number of process steps, and lowers fabrication costs while maintaining the ability to manufacture FinFET devices with the required precision and performance

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in high-quality silicon germanium fins with improved carrier mobility, reducing fabrication costs and defects, and ensuring uniformity and compatibility with FinFET device manufacturing processes.

Implementation Method 1

diffuse germanium atoms into a silicon substrate using a thermal treatment, forming a silicon germanium fin

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11978632B2Semiconductor device including a semiconductor fin comprising a silicon germanium portion and an isolation structure at a sidewall of the silicon germanium portion
Publication Date: 2024.05.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11978632B2 patent drawing
  • US11978632B2 patent drawing
  • US11978632B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate, an isolation structure, a gate structure, and a source/drain feature. The semiconductor substrate includes a semiconductor fin, wherein the semiconductor fin comprises a silicon germanium portion. The isolation structure is at a sidewall of a bottom portion of the silicon germanium portion. A top portion of the silicon germanium portion is higher than a top surface of the isolation structure, and an atomic concentration of germanium in the top portion of the silicon germanium portion is greater than an atomic concentration of germanium in the bottom portion of the silicon germanium portion. The gate structure is over a first portion of the silicon germanium portion of the semiconductor fin. The source/drain feature is over a second portion of the silicon germanium portion of the semiconductor fin.