SiGe FinFET Channel with Silicon Buffer Regions for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FinFET devices with silicon germanium channels experience increased off-state leakage current due to small valence band offset for holes, leading to higher power consumption, which is not effectively addressed by existing fabrication methods.
Innovation Solution
The method involves forming silicon germanium channel regions with silicon buffer regions by creating inner spacers that protect the silicon fin portions adjacent to the source/drain regions during oxidation, thereby separating the SiGe channel from the silicon source/drain regions and reducing excess leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon germanium channel regions are formed in finFET devices, then electron mobility and switching speed are improved, but off-state leakage current increases due to small valence band offset for holes
Solution Approach 1:
The fin structure is segmented into three distinct regions along its length: a silicon buffer region at the source/drain interface, a silicon germanium channel region in the middle, and another silicon buffer region at the other end. This segmentation allows each region to serve its specific function - the SiGe channel provides high electron mobility while the silicon buffer regions provide high valence band offset to suppress hole leakage current at the source/drain junctions.
Solution Approach 2:
Different material compositions are applied to different portions of the fin structure based on local functional requirements. The silicon germanium channel region is positioned where high electron mobility is needed for fast switching, while silicon buffer regions are positioned at the source/drain interfaces where high valence band offset is needed to suppress leakage. This local differentiation of material quality resolves the contradiction between speed and leakage suppression.
2Object-generated harmful factors
If inner spacers are used to protect silicon fin portions during oxidation, then silicon buffer regions are formed to suppress leakage, but fabrication process complexity increases
Solution Approach 1:
Inner spacers are formed on the fin structure before the oxidation process that creates the silicon germanium channel regions. These spacers are positioned to cover the portions of the fin that should become silicon buffer regions. By performing this protective action preliminarily, the subsequent oxidation process automatically forms the correct material distribution without requiring additional masking or patterning steps, thus managing fabrication complexity.
Solution Approach 2:
The inner spacers act as intermediary elements that mediate between the desired final structure (silicon buffer regions adjacent to source/drain) and the fabrication process. The spacers temporarily exist during fabrication to guide the oxidation process, and are later removed after serving their protective function. This intermediary approach simplifies the overall process compared to direct patterning of the buffer regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses leakage current, reducing power consumption in finFET devices by creating a silicon buffer region between the SiGe channel and source/drain regions, enhancing the performance of finFET devices.
Implementation Method 1
oxidizing the silicon germanium regions, such that the second portion of the silicon fin that is located adjacent to the silicon germanium regions is converted to a silicon germanium channel region during oxidizing of the silicon germanium regions
Data Source
AI summary
A method of forming a fin field effect transistor (finFET) device includes forming a silicon fin on a substrate; forming an inner spacer adjacent to a first portion of the silicon fin; forming silicon germanium regions adjacent to a second portion of the silicon fin and the inner spacer; and oxidizing the silicon germanium regions, such that the second portion of the silicon fin that is located adjacent to the silicon germanium regions is converted to a silicon germanium channel region during oxidizing of the silicon germanium regions, and such that the first portion of the silicon fin is protected by the inner spacer during oxidation of the silicon germanium regions, wherein the first portion of the silicon fin comprises a silicon buffer region located between the silicon germanium channel region and a source/drain region of the finFET device.