SiGe Fin Profile Control by Selective Etching Before Silicon Capping

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Solution Overview

Problem

Existing methods for forming silicon germanium (SiGe)-based channels in FETs are inadequate due to susceptibility to oxidation, leading to performance degradation, and existing trimming processes are not entirely satisfactory in achieving desired fin dimensions.

Innovation Solution

A method involving selective etching processes to trim Si-based and SiGe-based fins before depositing a silicon capping layer, ensuring precise fin dimensions and preventing oxidation, which includes measuring fin widths, determining the thickness of the silicon cap, and adjusting etching parameters to achieve target dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If selective etching processes are used to trim fins before depositing silicon capping layer, then fin dimension precision is improved and oxidation is prevented, but process complexity increases

Engineering Contradiction:

Improvefin dimension precisionVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fin trimming process is performed before depositing the silicon capping layer, establishing the final fin dimensions in advance. This preliminary action ensures that the fin dimensions are precisely controlled before the capping layer is formed, preventing oxidation and maintaining dimensional accuracy throughout subsequent processing steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The silicon capping layer serves as an intermediary protective layer deposited over the trimmed fins. This capping layer prevents oxidation of the fin structures while maintaining the precisely controlled dimensions achieved through the selective etching process, acting as a barrier between the fin and oxidizing environment.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If existing trimming processes are used for SiGe-based fins, then fin formation is achieved, but desired fin dimensions are not attained due to oxidation susceptibility

Engineering Contradiction:

Improvefin formationVSAvoidfin dimension accuracy

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The selective etching process for trimming SiGe-based fins is performed in an environment that prevents oxidation, and the subsequent deposition of silicon capping layer creates a protective atmosphere around the fin. This inert environment approach ensures that the fin dimensions remain accurate and free from oxidation-induced dimensional changes.

Inventive Principle:

Principle #39Inert atmosphere (Inert environment)

Solution Approach 2:

The structure comprises composite materials including SiGe-based fins trimmed to precise dimensions and covered with a silicon capping layer. This composite structure combines the beneficial properties of SiGe for device performance with the protective properties of silicon for oxidation resistance, achieving both ease of manufacture and dimensional precision.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the performance of FETs by preventing oxidation and maintaining precise fin dimensions, enhancing the stability and efficiency of the semiconductor device.

Implementation Method 1

A method involving selective etching processes to trim Si-based and SiGe-based fins before depositing a silicon capping layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

depositing a silicon capping layer, ensuring precise fin dimensions and preventing oxidation

Methodology Applied

Scientific EffectOxidation prevention: Oxidation

Data Source

PatentUS20230387213A1Silicon-germanium fins and methods of processing the same in field-effect transistors

Publication Date: 2023.11.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.