SiGe Fin Structure for Semiconductor Device Fabrication
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Solution Overview
Problem
Fin-structured semiconductor devices face challenges with fin collapse and unexpected removal during fabrication due to decreasing dimensions, and variations in channel widths affect device performance.
Innovation Solution
The use of a semiconductor device with fins made of different materials, such as silicon and germanium, to improve carrier mobility, allowing for relaxed size requirements and enhanced device performance by forming N and P channel devices with optimized gate structures and hard mask layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin dimensions are continuously decreased to improve device integration, then device density increases, but fin collapse and unexpected removal occur during fabrication
Solution Approach 1:
The patent changes the material composition parameter of the fin structure by incorporating SiGe semiconductor material with different Ge concentrations. This material parameter change enhances the mechanical strength and structural stability of the fin, preventing collapse during fabrication while maintaining reduced dimensions for high device integration density.
Solution Approach 2:
The patent employs composite semiconductor materials consisting of SiGe alloy with varying germanium concentrations within the fin structure. This composite material approach combines the benefits of silicon with the mechanical properties of germanium-containing materials, providing both the dimensional reduction capability and structural stability needed to prevent fin collapse during manufacturing processes.
2Device complexity
If fin height is increased to preserve gate space, then manufacturing complexity decreases, but device performance deteriorates due to carrier mobility limitations
Solution Approach 1:
The patent modifies the material composition parameter of the fin by incorporating SiGe semiconductor material, which fundamentally changes the carrier mobility characteristics. This allows the use of optimized fin heights that balance gate structure simplicity with improved carrier transport properties, eliminating the need for excessive height increases.
Solution Approach 2:
The patent applies different Ge concentrations at different locations within the fin structure (e.g., higher Ge concentration near the interface with source/drain regions). This local quality variation optimizes carrier mobility in critical regions while maintaining structural integrity, allowing for simplified gate structures without compromising device performance.
3Ease of manufacture
If single material fin structure is used to simplify manufacturing, then process complexity decreases, but device performance is limited by uniform carrier mobility
Solution Approach 1:
The patent implements local quality variation by incorporating SiGe material with different Ge concentrations at different positions within the fin structure. This allows optimization of carrier mobility in specific regions (such as near source/drain interfaces) while maintaining a relatively simple single-step fabrication process, thus balancing manufacturing ease with enhanced device performance.
Data Source
AI summary
A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers that is greater than a mobility of P-type carriers of the first semiconductor material. The second fin includes a layer formed of the first semiconductor material below the layer formed of the second semiconductor material. The semiconductor device further includes a hard mask layer disposed on the first and second fins and an insulator layer disposed below the first and second fins. The first and second semiconductor materials include silicon and germanium, respectively. The first and second fins are used to form respective N-channel and a P-channel semiconductor devices.