SiGe Fin Strain Engineering for Vertical pFET and nFET Channels
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Solution Overview
Problem
Vertical transport FETs face challenges in controlling strain in vertically standing SiGe channels on silicon substrates, leading to degradation of pFET performance due to tensile strain in the vertical direction and difficulties in achieving both tensile-strained and compressively-strained SiGe channels.
Innovation Solution
A method involving forming SiGe fins on a substrate, applying a protective layer and a germanium-containing layer, followed by an anneal at a temperature not exceeding 700°C in a nitrogen ambient, to selectively increase the germanium content on the surface of the SiGe fin, resulting in compressive strain for pFETs and maintaining tensile strain for nFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a germanium-containing layer is formed on the SiGe fin surface and annealed to increase surface germanium content, then compressive strain is achieved for pFET performance improvement, but the process complexity and manufacturing difficulty increase
Solution Approach 1:
A germanium-containing layer is deposited on the SiGe fin surface before final device formation. This preliminary action prepares the surface for selective germanium enrichment during annealing, enabling compressive strain to be introduced at the critical moment while keeping the overall process manageable through pre-planning
Solution Approach 2:
The germanium-containing layer is applied selectively to specific regions where compressive strain is needed (pFET regions), rather than uniformly across all fins. This local application allows differential strain engineering - compressive strain in pFETs while maintaining tensile strain in nFETs - thereby improving pFET performance without unnecessarily complicating the entire device structure
2Reliability
If selective germanium enrichment is performed on SiGe fin surfaces through annealing, then hole mobility and pFET performance are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The annealing process parameters (temperature, time, atmosphere) are carefully controlled and optimized to achieve the desired germanium redistribution. By adjusting these parameters, the process achieves sufficient germanium enrichment for improved hole mobility while maintaining manufacturability through well-established semiconductor processing techniques
Solution Approach 2:
The germanium-containing layer serves as an intermediary material that facilitates controlled germanium transfer to the SiGe fin surface during annealing. This intermediary layer enables precise control over the amount of germanium incorporated, achieving the required 20%+ increase in surface germanium content without requiring direct manipulation of the SiGe fin itself, thereby reducing manufacturing precision requirements
3Manufacturing precision
If the anneal temperature is kept at or below 700°C to prevent excessive germanium diffusion, then germanium content control is improved, but the energy consumption and process time increase
Solution Approach 1:
The annealing temperature is optimized to operate at or below 700°C, which is sufficient to activate germanium diffusion and achieve the desired surface enrichment while preventing excessive diffusion that would compromise germanium content control. This temperature optimization balances manufacturing precision with reasonable energy consumption by identifying the minimum effective temperature for the process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances hole mobility and performance by introducing compressive strain in the vertical direction of pFETs, while maintaining tensile strain in nFETs, thereby improving chip-level performance and overcoming the limitations of existing strain engineering techniques.
Implementation Method 1
performing an anneal to react the germanium-containing layer with a surface of the second SiGe fin such that the surface of the second SiGe fin includes a third amount of Ge which is at least 20% greater than the second amount
Implementation Method 2
the second SiGe fin includes a compressive strain in a vertical direction of at least 1 Gpa
Data Source
AI summary
A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.