Multi-Threshold Silicon Germanium FinFET Strain Engineering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) is reaching scaling limits, making it challenging to improve performance through traditional methods, and there is a need for enhanced semiconductor structures that can maintain electrostatic integrity and support high-mobility channels in FinFET devices.
Innovation Solution
A semiconductor structure is developed with multiple threshold voltage adjusted silicon germanium alloy fins, featuring different germanium contents and strains, formed by patterning silicon germanium alloy portions on insulator layers within a substrate, allowing for the creation of fin structures with distinct strain states to enhance channel material performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional scaling methods are used to miniaturize MOSFETs, then device dimensions are reduced, but performance improvement becomes difficult and electrostatic integrity is compromised
Solution Approach 1:
The device is segmented into multiple fins instead of a single planar channel, allowing the channel to be divided into vertically stacked conducting paths. This segmentation maintains electrostatic control by reducing the effective channel width while preserving drive current through parallel conduction paths
Solution Approach 2:
The device transitions from a two-dimensional planar structure to a three-dimensional vertical fin structure. By extending the channel into the vertical dimension, the device achieves better electrostatic control (reduced gate length effect) while maintaining large gate contact area through the vertical fin surface
2Reliability
If fin thickness is scaled down to maintain electrostatic integrity, then gate contact area is reduced, but this makes replacement metal gate process challenging
Solution Approach 1:
The gate contact area is extended into the vertical dimension by forming gates that wrap around the fin structures. This allows the gate to maintain large contact area with the channel while the fin thickness remains thin for electrostatic control, effectively decoupling these two requirements through three-dimensional geometry
3Length of moving object
If gate length is reduced to less than 20 nm for future technology nodes, then device scaling is achieved, but process tolerances for workfunction tuning layers become very tight
Solution Approach 1:
Instead of relying on precise thickness control of workfunction tuning layers (which becomes difficult at sub-20nm scales), the invention changes the approach by using strain engineering through silicon germanium alloy composition control. This shifts the critical parameter from nanometer-scale thickness tolerance to percentage-scale composition control, which is more manufacturable
4Shape
If thin metal layers are deposited conformally on fin sidewalls for FinFET devices, then three-dimensional structure is achieved, but this exacerbates the gate length scaling problem
Solution Approach 1:
The device is segmented into multiple fins with the gate deposited conformally on each fin sidewall. This segmentation allows the gate length to be effectively extended into the vertical dimension, maintaining control over the horizontal gate length while achieving the desired three-dimensional fin geometry for high drive current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the tuning of device threshold voltage for silicon germanium alloy channel materials with the same germanium content but different strain states, improving the performance of FinFET devices by boosting carrier mobility and maintaining electrostatic integrity, thus overcoming the limitations of traditional scaling methods.
Implementation Method 1
a first strain located on a surface of a first insulator layer portion and within a first device region of the substrate... a second strain located on a surface of a second insulator layer portion and within a second device region of the substrate... the first strain is different from the second strain
Data Source
AI summary
A semiconductor structure includes a first fin structure having a first strain located on a surface of a first insulator layer portion. The first fin structure includes a first doped silicon germanium alloy fin portion having a first germanium content and a silicon germanium alloy fin portion having a third germanium content. A second fin structure having a second strain is located on a surface of a second insulator layer portion. The second fin structure includes a second doped silicon germanium alloy fin portion having a second germanium content and a silicon germanium alloy fin portion having the third germanium content, wherein the first germanium content differs from the second germanium content and the third germanium content is greater than the first and second germanium contents, and wherein the first strain differs from the second strain.