SiGe FinFET Gate Dielectric Structure for Low Ge Diffusion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing transistor designs with SiGe channels face issues of increased gate leakage current and reduced carrier mobility due to Ge atom diffusion into the gate dielectric layer, leading to reliability and performance degradation.
Innovation Solution
A cap-free dielectric design is implemented, where a sacrificial semiconductor layer is used to accommodate Ge atoms during annealing, reducing Ge concentration in the dielectric layer and minimizing interface trap density, thereby improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional gate dielectric layer is used with SiGe channel, then the transistor structure is simple, but Ge atoms diffuse into the gate dielectric layer causing increased gate leakage current and reduced carrier mobility
Solution Approach 1:
A cap layer is introduced as an intermediary between the SiGe channel layer and the gate dielectric layer. This cap layer acts as a diffusion barrier that prevents Ge atoms from migrating into the gate dielectric during annealing processes, thereby reducing gate leakage current while maintaining the overall transistor structure
Solution Approach 2:
The cap layer is formed on the SiGe channel layer before the gate dielectric layer is deposited. This preliminary action prepares the surface by providing a Ge-containing layer that will accommodate Ge atoms during subsequent annealing, preventing Ge diffusion into the gate dielectric and reducing interface trap density
2Reliability
If a cap-free dielectric design is used, then Ge diffusion is minimized and carrier mobility is enhanced, but the process complexity increases due to additional sacrificial layer steps
Solution Approach 1:
The cap layer is selectively removed after serving its purpose as a Ge diffusion barrier and accommodation layer. This extraction of the sacrificial cap layer eliminates the need for a permanent cap structure, achieving low Ge concentration in the gate dielectric interface and high carrier mobility in the SiGe channel
Solution Approach 2:
The Ge concentration profile is controlled by adjusting the cap layer thickness and annealing parameters. By optimizing these parameters, the cap layer effectively captures Ge atoms during annealing, preventing Ge diffusion into the gate dielectric while maintaining SiGe channel quality for high carrier mobility
3Quantity of substance
If the cap layer thickness is increased, then Ge atom accommodation capacity is improved, but the interface trap density increases due to thicker dielectric layer
Solution Approach 1:
The cap layer thickness is optimized to balance Ge atom accommodation capacity with interface quality. The thickness is controlled within a specific range that provides sufficient Ge atom capture capability while maintaining a thin enough structure to minimize interface trap density and preserve carrier mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cap-free design reduces gate leakage current and enhances carrier mobility by minimizing Ge diffusion and interface states, resulting in improved transistor reliability and performance.
Implementation Method 1
Ge atom diffusion into the gate dielectric layer
Implementation Method 2
during annealing
Data Source
AI summary
A semiconductor structure includes a first fin structure and a second fin structure. A first gate electrode disposed over the first fin structure, and a second gate electrode disposed over the second fin structure. A dielectric layer disposed between the first fin structure and the first gate electrode, and between the second fin structure and the second gate electrode. A Ge concentration in an interface between the dielectric layer and the second fin structure is less than 25%.