Bulk SiGe FinFET With Germanium Gradient Substrate

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Solution Overview

Problem

SiGe FinFET devices on bulk silicon substrates face dislocation defects at the SiGe/silicon interface due to exceeding the critical thickness, leading to excessive junction leakage and potential shorts between source and drain.

Innovation Solution

A method is developed to form a bulk SiGe FinFET with a SiGe gradient in the substrate, where the SiGe/silicon interface is pushed away from the device region by epitaxially growing a thin SiGe layer on silicon fins, converting the silicon substrate to SiGe, and forming a punchthrough stop and shallow trench isolation, ensuring dislocations are outside the device area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SiGe fins are grown thicker to improve device performance, then PFET performance improves, but dislocation defects occur at the SiGe/silicon interface

Engineering Contradiction:
ImprovePFET performanceVSAvoiddislocation defects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by creating a continuous germanium concentration gradient in the substrate, where the germanium percentage varies from 0% at the surface to a maximum value deeper in the substrate. This gradual parameter change in composition allows the SiGe fins to be grown thicker without generating dislocation defects, as the gradient accommodates the lattice mismatch progressively rather than abruptly at a single interface.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements local quality by having different germanium concentrations at different depths of the substrate. The region near the surface has lower germanium content while deeper regions have higher germanium content, creating locally optimized conditions that prevent dislocations while maintaining the desired fin thickness for improved PFET performance.

Inventive Principle:
Principle #3Local quality

2Reliability

If SiGe fins are grown thicker to improve device performance, then channel control improves, but junction leakage increases due to dislocations

Engineering Contradiction:
Improvechannel controlVSAvoidjunction leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

By implementing a continuous germanium concentration gradient rather than a sharp interface, the patent eliminates dislocation defects that would otherwise cause junction leakage. This allows thicker SiGe fins to be grown, improving channel control, while the gradient structure prevents the formation of defect pathways that lead to leakage.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If a sharp SiGe/silicon interface is used to simplify manufacturing, then process complexity is reduced, but dislocation defects occur exceeding critical thickness

Engineering Contradiction:
Improveinterface formationVSAvoiddislocation control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent replaces the sharp interface with a continuous gradient profile, where germanium concentration changes progressively with depth. This approach maintains manufacturing simplicity while achieving precise control over dislocation formation, allowing the structure to accommodate thicker fins without defects.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively isolates dislocations from the device region, preventing junction leakage and dopant diffusion issues, thereby enhancing the reliability and performance of SiGe FinFET devices.

Implementation Method 1

heating the silicon fins and the bulk silicon substrate in an oxygen ambient to cause the Ge of the SiGe layer to react with the silicon in the silicon fins and a top portion of the bulk silicon substrate to form SiGe

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

epitaxially growing a SiGe layer on the silicon fins and on the bulk silicon substrate

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9735155B2Bulk silicon germanium FinFET
Publication Date: 2017.08.15 ADEIA SEMICONDUCTOR SOLUTIONS LLC
  • US9735155B2 patent drawing
  • US9735155B2 patent drawing
  • US9735155B2 patent drawing

AI summary

A bulk SiGe FinFET which includes: a plurality of SiGe fins and a bulk semiconductor substrate, the SiGe fins extending from the bulk semiconductor substrate; the SiGe fins having a top portion and a bottom portion, a part of the bottom portion being doped to form a punchthrough stop; the bulk semiconductor substrate having a top portion in contact with the SiGe fins and comprising a gradient of germanium and silicon, and a bottom portion of silicon in contact with the top portion such that the gradient has a composition of SiGe at the top portion in contact with the SiGe fins that is the same composition of SiGe as in the SiGe fins, the proportion of germanium atoms in the gradient gradually decreasing and the proportion of silicon atoms in the gradient gradually increasing in the gradient until the top portion contacts the bottom portion.