SiGe:GaB Source-Drain Structures for Ultra-Low PMOS Resistivity
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Solution Overview
Problem
Conventional fabrication processes face challenges in achieving ultra-low resistivity in source and drain structures for integrated circuits, particularly in the 10 nanometer node or sub-10 nanometer range, limiting the scalability and performance of semiconductor devices.
Innovation Solution
The implementation of gallium and boron co-doped silicon germanium (SiGe:GaB) source or drain structures, combined with a laser anneal process, to minimize implant damage and enhance active dopant incorporation, resulting in resistivity below 2E-9 Ohm cm2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but resistivity cannot be reduced below a certain threshold
Solution Approach 1:
The fabrication process is divided into distinct stages: ion implantation followed by selective laser annealing. This segmentation allows each process to be optimized independently - the implantation process deposits dopants while the laser annealing process selectively activates them in specific regions, achieving ultra-low resistivity through controlled spatial separation of functions
Solution Approach 2:
The invention changes the physical state and parameters of the semiconductor material through controlled laser heating. By adjusting laser parameters (energy density, pulse duration, wavelength) and implantation parameters (dopant type, concentration, energy), the material transitions from as-implanted state to annealed state, achieving resistivity reduction below 2E-9 Ohm-cm2
2Manufacturing precision
If ion implantation is used to reduce resistivity, then active dopant incorporation increases, but implant damage is introduced
Solution Approach 1:
The invention converts the harmful implant damage into a beneficial process by using selective laser annealing. The laser energy selectively melts and recrystallizes the damaged regions, simultaneously activating the dopants and repairing the crystal structure. This transforms the previously harmful implant damage into an opportunity for controlled dopant activation and damage recovery in a single localized process step
3Productivity
If feature size is scaled down to increase device density, then capacity increases, but performance optimization becomes increasingly difficult
Solution Approach 1:
The selective laser annealing process applies different thermal treatments to different regions of the semiconductor structure. By controlling the laser parameters, the process creates locally optimized zones with ultra-low resistivity in the source/drain regions while maintaining appropriate properties in the channel and other areas. This local quality control enables performance optimization even as overall device dimensions scale down
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves ultra-low resistivity in PMOS transistors, improving drive currents and reducing implant damage, suitable for advanced integrated circuit structures including FINFET, gate-all-around, and backside contact architectures.
Implementation Method 1
combined with a laser anneal process, to minimize implant damage and enhance active dopant incorporation
Implementation Method 2
gallium and boron co-doped silicon germanium (SiGe:GaB) source or drain structures
Data Source
AI summary
Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.