SiGe:GaB Source-Drain Structures for Low Contact Resistivity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit fabrication processes face challenges in achieving low resistivity for source and drain structures, particularly at the 10 nanometer node or below, due to variability and implant damage issues, which limits further scaling and performance optimization.
Innovation Solution
The use of gallium and boron co-doped silicon germanium (SiGe:GaB) source or drain structures, combined with laser anneal for implant damage mitigation, to achieve ultra-low resistivity levels less than 2E-9 Ohm cm, through co-implantation followed by a short pulse laser anneal process before titanium deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for source and drain structures, then manufacturing simplicity is maintained, but resistivity remains high and variability increases at 10 nanometer node or below
Solution Approach 1:
The patent applies parameter changes by modifying the dopant composition (using gallium and boron co-doping instead of conventional single dopants) and doping concentration in the source and drain structures. This enables achieving resistivity below 2E-9 Ohm cm at 10 nanometer node and below, resolving the contradiction between maintaining manufacturing simplicity and achieving precise resistivity control.
Solution Approach 2:
The patent employs composite materials through the use of silicon germanium (SiGe) as the base material combined with dual dopants (gallium and boron). This composite approach enables superior electrical properties and reduced variability compared to conventional materials, addressing the resistivity control challenge without proportionally increasing process complexity.
2Manufacturing precision
If doping concentration is increased to reduce resistivity, then electrical conductivity improves, but implant damage increases
Solution Approach 1:
The patent replaces the conventional thermal annealing process with a laser annealing process. This substitution enables precise control of the annealing conditions, activating dopants while minimizing implant damage and preventing excessive diffusion. The laser annealing achieves resistivity below 2E-9 Ohm cm while reducing the harmful effects of implant damage compared to traditional thermal methods.
3Productivity
If feature size is scaled down to increase device density, then capacity increases, but variability in fabrication processes worsens
Solution Approach 1:
The patent implements parameter changes by using dual dopant co-doping (gallium and boron) with optimized concentration ratios and applying laser annealing with controlled pulse duration and energy density. These parameter optimizations reduce process variability and achieve consistent resistivity below 2E-9 Ohm cm across scaled features at 10 nanometer node and below, enabling higher device density without proportionally increasing variability.
4Manufacturing precision
If laser anneal is applied to reduce implant damage, then dopant activation improves, but process time and energy consumption increase
Solution Approach 1:
The patent employs periodic action through pulsed laser annealing instead of continuous heating. The pulsed laser delivers energy in short, controlled bursts, enabling rapid dopant activation with minimal thermal diffusion. This approach achieves superior dopant activation and reduced implant damage while keeping the overall process time comparable to or shorter than conventional thermal annealing, resolving the contradiction between activation quality and time consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved active dopant incorporation, minimal diffusion, and higher PMOS drive currents, effectively reducing contact resistivity and enhancing the performance of integrated circuit structures.
Implementation Method 1
combined with laser anneal for implant damage mitigation
Implementation Method 2
followed by a short pulse laser anneal process
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A~2B
AI summary
Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.