SiGe Gradient Annealing for CMOS Electron and Hole Conduction
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Solution Overview
Problem
The coexistence of N-channel and P-channel field effect transistors on the same semiconductor substrate is challenging due to the difficulty in growing SiGe layers with uniform germanium concentration, leading to inefficient charge carrier mobility and threshold voltage management in CMOS technology.
Innovation Solution
A manufacturing method involving a multilayer structure with a silicon-germanium layer subjected to laser annealing, creating a germanium concentration gradient in specific regions to optimize electron and hole conduction zones, allowing for the co-integration of N-channel and P-channel transistors with improved mobility and reduced threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective oxidation is used to transform silicon layer into silicon-germanium portion, then germanium atoms are repelled and concentrated in desired regions, but the manufacturing process becomes complex with multiple steps including epitaxial growth, oxidation, and removal of oxide layer
Solution Approach 1:
The patent extracts the germanium concentration control step from the complex selective oxidation process. By using ion implantation to directly introduce germanium ions into specific regions, the method eliminates the need for epitaxial growth, oxidation, and oxide removal steps, while achieving precise germanium concentration distribution in the silicon layer
Solution Approach 2:
The patent replaces the chemical oxidation-based germanium concentration control with a physical ion implantation method. This substitution allows direct control of germanium concentration through ion dose and energy parameters, avoiding the complex multi-step chemical processes while achieving the same or better precision
2Manufacturing precision
If SiGe layer is grown only in regions where PMOS transistors are desired, then localised germanium condensation is achieved, but the epitaxial growth process becomes difficult to control and manufacture
Solution Approach 1:
The patent applies local quality by using ion implantation to introduce germanium ions only into specific regions where PMOS transistors are desired. By controlling the ion implantation parameters (dose, energy, and masking), precise local germanium concentration profiles are achieved without the difficulty of controlling localized epitaxial growth
Solution Approach 2:
The patent replaces the difficult-to-control localized epitaxial growth with ion implantation, a well-established and easily controllable physical process. The ion implantation method allows precise control of germanium concentration and distribution through standard semiconductor manufacturing equipment and parameters
3Reliability
If nanosecond laser annealing is used to concentrate germanium atoms at the surface, then charge carrier mobility is improved, but the germanium concentration gradient creates non-uniform distribution across the SiGe layer thickness
Solution Approach 1:
The patent applies preliminary action by first introducing germanium ions uniformly throughout the silicon layer thickness using ion implantation, then using selective laser annealing to concentrate germanium at specific depths. This two-step approach ensures both uniform initial distribution and subsequent localized concentration where needed
Solution Approach 2:
The patent uses periodic action through selective laser annealing pulses applied to different regions of the silicon layer. By controlling the laser pulse timing and positioning, germanium atoms are redistributed in a controlled manner to achieve desired concentration profiles while maintaining overall composition stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process and enhances the performance of both N-channel and P-channel transistors by optimizing charge carrier mobility and reducing electrical resistivity, facilitating the co-integration of N-channel and P-channel transistors on the same substrate.
Implementation Method 1
subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the second region
Implementation Method 2
A redistribution of germanium atoms is observed during recrystallisation of the SiGe layer. The germanium atoms are concentrated towards the surface of the SiGe layer, due to a segregation mechanism.
Implementation Method 3
This technique comprises a step of epitaxially growing a layer of SiGe on the portion of silicon layer to be transformed
Implementation Method 4
a step of oxidising the SiGe layer. This oxidation step, known as 'selective' with respect to silicon, has the effect of repelling germanium atoms in the underlying silicon layer while forming a layer of silicon oxide (SiO2) on the surface
Data Source
AI summary
A method for manufacturing a semiconductor device including a first semiconductor zone optimised for electron conduction and a second semiconductor zone optimised for hole conduction, the method including providing a multilayer structure including a substrate and a silicon-germanium layer disposed on the substrate; defining in the multilayer structure a first region for containing the first semiconductor zone and a second region for containing the second semiconductor zone, and subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the second region, the portion including prior to laser annealing a part of the silicon-germanium layer, the portion having after laser annealing a germanium concentration gradient with a germanium concentration which increases towards an upper face of the portion.