SiGe HBT Collector Segmentation for Breakdown Voltage
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Solution Overview
Problem
High-voltage silicon-germanium heterojunction bipolar transistors (SiGe HBTs) integrated with CMOS devices face a significant drop in breakdown voltage due to thermal processes, leading to increased device resistance and saturation voltage drop, as pseudo buried layers diffuse into the collector region.
Innovation Solution
The SiGe HBT is formed on a P-type silicon substrate with a collector region extending into field oxide regions, pseudo buried layers separated from the active area, and deep hole contacts with specific ion implantation conditions to adjust breakdown voltage and reduce resistance, featuring N-type ion implantation regions and a P-type silicon-germanium epitaxial base region with optimized doping and geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pseudo buried layers are formed at the bottom of field oxide regions and directly connected to collector region, then manufacturing simplicity is improved, but breakdown voltage drops due to thermal diffusion during CMOS processes
Solution Approach 1:
The collector region is divided into two parts: a main collector region in the active area and an extended collector region that laterally extends into the field oxide regions. This segmentation allows the extended region to provide thermal isolation for the pseudo buried layers while the main collector region maintains electrical connection, thus resolving the contradiction between manufacturing simplicity and breakdown voltage maintenance.
Solution Approach 2:
The extended collector region acts as an intermediary structure between the pseudo buried layers and the main collector region. It provides a controlled pathway for electrical connection while simultaneously serving as a thermal barrier to prevent excessive diffusion of pseudo buried layers into the active collector region during CMOS thermal processes.
2Reliability
If pseudo buried layers are positioned farther from the collector region to reduce diffusion, then breakdown voltage is improved, but device resistance increases due to lengthened current paths
Solution Approach 1:
The collector region extends laterally in the horizontal dimension into the field oxide regions, rather than only increasing vertical depth. This dimensional change allows the current path to be lengthened in a controlled manner while the extended region's high doping concentration maintains low resistance, thus improving breakdown voltage without excessively increasing device resistance.
Solution Approach 2:
The extended collector region has different local properties compared to the main collector region: it is located in the field oxide region (different dielectric environment) and has optimized doping concentration. This local quality differentiation allows it to serve dual functions: providing thermal isolation to improve breakdown voltage while maintaining adequate electrical conductivity through controlled doping.
3Reliability
If collector region depth is increased to improve breakdown voltage, then device resistance increases due to longer current paths
Solution Approach 1:
The collector region structure is made dynamic and adaptable: it includes both a vertical depth component and a lateral extension component. The lateral extension into the field oxide regions can be optimized independently of the vertical depth, allowing flexible adjustment of the structure to balance breakdown voltage requirements with resistance minimization based on specific application needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for adjustable breakdown voltage, maintains high breakdown voltage even with CMOS thermal processes, shortens current paths, and reduces resistance and saturation voltage drop, enhancing the performance of SiGe HBTs.
Implementation Method 1
A collector region, composed of an N-type ion implantation region formed in the active area
Implementation Method 2
Pseudo buried layers, composed of N-type ion implantation regions formed at the bottom of the field oxide regions
Data Source
AI summary
A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.