SiGe HBT and SCR Integration for High Voltage ESD Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in integrating high voltage elements, such as silicon controlled rectifiers (SCRs), into CMOS or BiCMOS SiGe/SiGeC systems without additional processing steps or increased costs, particularly for applications requiring voltage control above 40 V, where standard CMOS technology lacks the necessary breakdown voltages for ESD networks.
Innovation Solution
An integrated semiconductor device is developed, featuring a heterojunction bipolar transistor (HBT) with a SiGe or SiGeC base region and a trench-biased PNPN silicon controlled rectifier (SCR) with a SiGe or SiGeC interconnect, allowing for the integration of high voltage elements within the same semiconductor substrate using a common process, reducing processing time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard CMOS technology is used, then manufacturing cost and processing time are reduced, but breakdown voltage is insufficient for high voltage applications above 40 V
Solution Approach 1:
The patent merges bipolar processing steps with conventional CMOS processing into a unified process flow. The SiGe layer is deposited and patterned to serve dual purposes: forming HBT base regions and creating interconnect straps for high voltage devices, eliminating the need for separate bipolar processing streams and reducing overall manufacturing complexity
Solution Approach 2:
The SiGe layer performs multiple functions within the same process: it serves as the base region material for HBT devices, provides high voltage interconnect straps for SCR and LDMOS devices, and enables both low voltage CMOS and high voltage device integration on the same substrate without requiring additional processing steps
2Reliability
If bipolar processing steps are isolated from CMOS processing steps, then implant and process issues between MOSFETs and bipolar transistors are avoided, but processing time and manufacturing costs increase
Solution Approach 1:
The patent combines previously separate bipolar and CMOS processing streams into a single integrated process. The SiGe layer deposition and patterning steps are performed once to simultaneously define both HBT base regions and high voltage interconnect straps, eliminating redundant processing steps and reducing total fabrication time
Solution Approach 2:
The SiGe layer is deposited and patterned early in the process flow before final device formation steps. This preliminary action establishes both the HBT base regions and the high voltage interconnect straps in advance, allowing subsequent processing to proceed without additional masking or patterning steps for these critical structures
3Reliability
If additional processing steps are required for forming bipolar transistors, then device performance is improved, but manufacturing costs and processing time increase
Solution Approach 1:
The SiGe layer serves multiple device formation functions: it creates the base region for HBT devices requiring high performance, provides high voltage interconnect straps for SCR and LDMOS devices, and integrates all these functions into a single deposition and patterning sequence, maintaining high device performance without sacrificing manufacturing efficiency
Solution Approach 2:
The patent utilizes variations in SiGe layer parameters (composition, thickness, doping) to achieve different device functions from the same base material layer, allowing high performance bipolar devices and high voltage devices to be formed using the same processing steps with different parameter settings
4Adaptability or versatility
If high voltage elements are integrated into CMOS systems, then system functionality is improved, but additional masking steps and costs are required
Solution Approach 1:
The SiGe layer performs dual functions as both HBT base material and high voltage interconnect strap material, allowing integration of high voltage elements into CMOS systems without requiring separate processing streams or additional masking steps beyond what is already needed for HBT formation
Solution Approach 2:
The patent merges the formation of HBT base regions and high voltage interconnect straps into a single patterning step, where the same photoresist mask and etch process define both structures, thereby integrating high voltage functionality without increasing processing complexity
Data Source
AI summary
The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.