SiGe Interfacial Layer for FinFET Epitaxial Growth Control
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Solution Overview
Problem
In the semiconductor industry, particularly in FinFET device manufacturing, the decreasing scale presents challenges such as surface impurity effects and non-uniform epitaxial source/drain region growth due to high aspect ratios and intricate three-dimensional designs, which affect device performance and reliability.
Innovation Solution
An interfacial layer comprising silicon germanium (SiGe) is formed along the surfaces of recesses in the fins, suppressing surface impurities and ensuring uniform growth of the epitaxial source/drain regions by encapsulating impurities and maintaining a smooth surface, thereby enhancing the epitaxial growth and strain characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the scale is decreased to increase device density, then higher device density is achieved, but surface impurity effects become more significant and device performance deteriorates
Solution Approach 1:
An interfacial layer is introduced between the fin structure and the epitaxial source/drain region. This interfacial layer acts as an intermediary that suppresses surface impurity effects during epitaxial growth, allowing high device density to be achieved without the detrimental impact of surface impurities on device performance
2Ease of manufacture
If recesses are formed in fins to enable epitaxial growth, then source/drain regions can be formed, but surface roughness increases and crystal dislocations occur
Solution Approach 1:
The interfacial layer is formed in advance within the recesses of the fin structures before the epitaxial source/drain regions are grown. This preliminary action prepares the surface by providing a smooth interface that prevents surface roughness and crystal dislocations during the subsequent epitaxial growth process
3Speed
If high aspect ratio fins are used to increase surface area, then faster and better-controlled transistors are achieved, but non-uniform epitaxial growth occurs
Solution Approach 1:
The interfacial layer is selectively formed in the recesses of the high aspect ratio fins, providing localized quality improvement at the critical growth interface. This ensures uniform epitaxial growth in the regions where it is most needed, while maintaining the high aspect ratio geometry required for fast transistor switching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interfacial layer effectively reduces surface roughness and crystal dislocations, leading to improved conductivity and uniformity of the epitaxial source/drain regions, which enhances the performance and reliability of FinFET devices by controlling the growth and strain transfer to the channel.
Implementation Method 1
ensuring uniform growth of the epitaxial source/drain regions
Data Source
AI summary
An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.