SiGe Epitaxial Layer Thickness Uniformity in Semiconductor Devices
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Solution Overview
Problem
The uniform growth of silicon-germanium (SiGe) layers in semiconductor integrated circuit devices is challenging due to differences in spacing between gate patterns, leading to varying compressive stresses and reliability issues in semiconductor devices.
Innovation Solution
The method involves forming gate patterns with different spacings on a substrate, followed by the sequential growth of SiGe epitaxial layers using different silicon source gases to achieve varying thicknesses in source/drain trenches, ensuring uniformity and reliability across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SiGe is grown on regions with different gate pattern spacings, then the growth process can be simplified, but the SiGe layer thickness becomes non-uniform leading to varying compressive stresses and reliability issues
Solution Approach 1:
The patent applies local quality by using different silicon source gases for different regions: a first silicon source gas (e.g., silane) for the first region with narrower gate spacing and a second silicon source gas (e.g., dichlorosilane) for the second region with wider gate spacing. This regional differentiation enables precise control of SiGe layer thickness in each area, achieving uniform compressive stress despite varying gate pattern spacings.
2Manufacturing precision
If the SiGe layer thickness is made uniform across all regions, then compressive stress uniformity is achieved, but the manufacturing process becomes more complex requiring different source gases
Solution Approach 1:
The patent employs parameter changes by varying the silicon source gas type based on regional requirements. The first silicon source gas and second silicon source gas have different chemical properties and deposition characteristics, allowing optimization of SiGe growth rate and thickness control for each region's specific gate spacing conditions, thereby achieving uniform thickness despite process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent SiGe epitaxial layer thicknesses across regions with different gate pattern spacings, enhancing the reliability and performance of semiconductor integrated circuit devices by controlling compressive stresses.
Implementation Method 1
A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas
Data Source
AI summary
Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.