SiGe Nanosheet Channel Shaping for 3D Backside Power Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor device fabrication technologies face challenges in scaling beyond single digit nanometer nodes due to constraints in transistor density and integration of backside power and signal wiring, particularly with buried power rails, leading to issues like constrained width, metallization variability, and difficult connections to source and drain contacts.
Innovation Solution
A method involving wafer bonding and epitaxial layer stacking to form stacked transistors with backside power rails and signal wiring, allowing for wider power rails and improved connections through dielectric layers, enabling flexible backside wiring and reduced parasitic resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional 2D fabrication with buried power rails is used, then manufacturing process is simpler, but power rail width is constrained and connections to source/drain contacts are difficult
Solution Approach 1:
The patent transitions from traditional 2D planar fabrication to 3D stacked architecture, enabling power rails to extend in the vertical dimension through multiple tiers. This dimensional change allows power rails to achieve greater effective width and surface area for connections without constraining lateral space, while the stacking approach manages complexity through modular layering of functional blocks
Solution Approach 2:
The fabrication process is segmented into distinct tiers and layers, with each tier containing specific functional blocks (logic, memory, I/O). This segmentation allows independent optimization of power distribution at each level and simplifies the overall manufacturing by breaking down the complex 3D integration into manageable sequential steps
2Productivity
If transistor scaling continues in 2D circuits, then transistor density increases, but scaling challenges intensify at single digit nanometer nodes
Solution Approach 1:
The patent moves from 2D planar transistor scaling to 3D stacked transistor architectures, where multiple transistor layers are vertically integrated. This enables continued increases in transistor density by utilizing the vertical dimension rather than relying solely on lateral scaling, thereby avoiding the diminishing returns and precision challenges at single digit nanometer nodes
Solution Approach 2:
Multiple tiers of transistors are nested vertically, with each tier containing stacked transistor layers. This nesting approach packs more transistors into a smaller footprint by utilizing vertical space, achieving higher density without requiring further lateral scaling that would demand increasingly precise manufacturing
3Reliability
If backside power rails are implemented in traditional architecture, then power delivery is improved, but metallization variability and connection difficulty increase
Solution Approach 1:
The patent implements power rails in multiple vertical tiers rather than a single backside layer, distributing power delivery across different height levels. This multi-dimensional approach reduces metallization variability by providing multiple parallel power paths and improves connection reliability through distributed contact points across different tiers
Solution Approach 2:
Each tier is equipped with its own power rails and interconnect structures tailored to the specific power requirements of the functional blocks at that level. This localized power distribution optimizes metallization consistency for each tier's specific needs rather than using a uniform approach across the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances transistor density and reduces parasitic resistances by providing wider power rails and improved interconnects, facilitating further reductions in standard cell height and enabling advanced semiconductor device integration.
Implementation Method 1
bonding a first wafer to a second wafer via a first bonding dielectric layer
Implementation Method 2
a first stack of alternating layers of epitaxially grown semiconductor layers formed over a second bulk semiconductor material
Implementation Method 3
The second bulk semiconductor material is removed to uncover the first stack
Implementation Method 4
backside power rails in contact with vias that extend through the first bonding dielectric layer
Data Source
AI summary
A semiconductor device includes a tier of transistors and devices. Each transistor includes a respective channel structure including a first epitaxially grown semiconductor material, a respective shell structure all around a respective middle portion of the respective channel structure, a respective gate structure all around the respective shell structure, and respective source/drain (S/D) structures on respective opposing ends of the respective channel structure. The respective middle portion of each channel structure has a smaller circumference than the respective opposing ends of each channel structure when viewed from a respective current direction in the channel structure. The respective shell structure is formed of a semiconductor material having lattice mismatch with the first epitaxially grown semiconductor material.