GAA SiGe Nanosheet Channel With Common SDE to Cut Parasitic Resistance
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Solution Overview
Problem
The use of non-planar semiconductor devices like FinFETs faces challenges in forming source/drain regions with high parasitic resistance due to barriers between the channel and source/drain regions, which hinders efficient performance beyond the 7 nm technology node.
Innovation Solution
A gate-all-around nanosheet device is fabricated with a continuous silicon germanium channel spanning from the source to the drain, using alternating stacks of Si and SiGe layers, recessing, and forming inner spacers to create a controlled source/drain extension structure with undoped SiGe regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain regions are formed by epitaxial growth from exposed substrate and nanosheet sidewalls, then device structure is achieved, but high parasitic resistance occurs due to barriers between channel and source/drain regions
Solution Approach 1:
The patent merges the channel and source/drain extension regions into a continuous silicon germanium material structure. The SDE region is formed from the same SiGe material as the channel, eliminating the material barrier that causes parasitic resistance. This merging allows seamless carrier transport between source/drain and channel regions.
Solution Approach 2:
The patent applies local quality by creating a doped silicon germanium layer specifically in the source/drain extension region while maintaining undoped SiGe in the channel portion. This localized doping provides the necessary electrical properties for source/drain contact while preserving the channel's carrier transport characteristics, thus reducing parasitic resistance without compromising channel performance.
2Shape
If alternating stacks of Si and SiGe layers are used to form nanosheets, then nanosheet structure is achieved, but complex fabrication process is required
Solution Approach 1:
The patent segments the nanosheet structure into distinct functional regions: suspended SiGe channel nanosheets and doped SiGe source/drain extension regions. The inner gate spacers further segment the channel into portions under gate control and portions forming SDE regions. This segmentation allows selective processing and material properties in different regions while maintaining overall structural integrity.
Solution Approach 2:
The patent performs preliminary actions by forming the doped SiGe layer and inner gate spacers before final nanosheet release and functional gate formation. The SDE regions are pre-formed with appropriate doping and geometry, and inner gate spacers are positioned in advance to define subsequent etching patterns. These preliminary structures guide the final device formation and reduce later processing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates high parasitic resistance and potential barriers, enhancing device performance by creating a continuous channel with reduced resistance and improved conductivity.
Implementation Method 1
Nanosheet formation relies on the selective removal of one semiconductor material (e.g., silicon) to another semiconductor material (e.g., a silicon germanium alloy) to form suspended nanosheets for gate-all-around devices
Implementation Method 2
forming a source/drain region by epitaxial growth of a semiconductor material on the physically exposed sidewalls of the thin-doped SiGe layer
Implementation Method 3
performing a thermal mix, resulting in the undoped SiGe, the thin-doped SiGe, and each semiconductor channel becoming one or more silicon germanium (SiGe) semiconductor channel material nanosheets
Data Source
AI summary
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of sacrificial and semiconductor channel material nanosheets on a substrate is provided, where: a sacrificial gate structure and dielectric spacer material layer straddle over the stack. End portions of each of the sacrificial nanosheets are recessed. A thin-doped SiGe layer is formed on exposed surfaces of the semiconductor channel material nanosheet. A dielectric spacer material layer is formed within each gap. A source/drain region is formed. The sacrificial gate structure is removed. Each sacrificial semiconductor material nanosheet is removed. Exposed portions of each semiconductor channel material nanosheet are trimmed. Undoped SiGe is formed on exposed portions of each semiconductor channel. A thermal mix is performed, forming one or more SiGe nanosheets. A functional gate structure is formed, where the functional gate structure wraps around each suspended SiGe nanosheet.