SiGe Nanostructure Charge Trap for Memory Scaling
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Solution Overview
Problem
Charge retention issues in charge trap flash (CTF) memory devices due to defects in the tunneling dielectric layer, which limit further scaling and reduce charge retention capabilities.
Innovation Solution
A memory device with a vertical stack of alternating oxide and nitride layers, featuring silicon germanium (SiGe) nanostructures selectively grown on the nitride layer, encapsulated by a gate oxide layer, which enhances charge retention and allows for a thinner gate oxide layer, reducing operating voltages and improving program/erase speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the tunneling dielectric layer is reduced to scale down device size, then device scaling is improved, but charge retention capability deteriorates due to increased defect risk
Solution Approach 1:
The patent introduces a charge trapping layer as an intermediary between the tunneling dielectric layer and the floating gate. This charge trapping layer captures and holds charges that would otherwise leak through defects in the thin tunneling dielectric, thereby maintaining charge retention capability while allowing the tunneling dielectric to be scaled down to reduce device size.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including the tunneling dielectric layer, charge trapping layer, and floating gate. This composite architecture combines the advantages of thin tunneling dielectric for scaling with the charge retention benefits of the charge trapping layer, resolving the contradiction between device size reduction and charge retention maintenance.
2Reliability
If a charge trapping layer is introduced to improve charge retention, then charge retention capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the charge trapping function with the existing floating gate structure by positioning the charge trapping layer between the tunneling dielectric and the floating gate. This integration allows the charge trapping layer to work in conjunction with the floating gate rather than as a separate, additional component, thereby improving charge retention while limiting the increase in device complexity.
3Quantity of substance
If device size is reduced to increase memory capacity, then memory capacity is improved, but charge retention capability deteriorates due to thinner tunneling dielectric
Solution Approach 1:
The charge trapping layer serves as a mediator that compensates for the reduced charge retention capability caused by the thinner tunneling dielectric in scaled-down devices. By capturing and retaining charges, this layer enables higher memory capacity through device scaling while maintaining adequate charge retention performance.
Solution Approach 2:
The patent uses a composite multi-layer structure that combines thin tunneling dielectric for scaling with charge trapping layer for retention, enabling both increased memory capacity and maintained charge retention capability in the scaled device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of SiGe nanostructures embedded in the charge trapping layer improves charge retention, addresses defects in the tunneling dielectric layer, and enables smaller device sizes with better endurance and faster programming/erasing.
Implementation Method 1
a charge trap layer instead of a floating gate has been developed. The CTF memory device may utilize a shifting threshold voltage as charges are trapped in the charge trap layer
Implementation Method 2
a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer
Implementation Method 3
a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough
Data Source
AI summary
Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).