SiGe-Cladded PFET Channel Structure for Higher 3D Transistor Density
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Solution Overview
Problem
The complexity of gate metal processes in three-dimensional integrated circuit devices with high aspect ratios due to the vertical positioning of nFET and pFET transistors hinders the efficient concentration of transistors within a small area.
Innovation Solution
The integration of p-type field effect transistors with strained channels, comprising a silicon channel and silicon germanium cladding layers on opposing surfaces, where the silicon germanium cladding layers are epitaxially grown from adjacent sacrificial layers, simplifying the fabrication process without increasing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional device structures are used to concentrate more transistors within the same area, then transistor density is improved, but gate metal process complexity increases due to high aspect ratios
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional stacked transistor structures, utilizing the vertical dimension to increase transistor density. Multiple transistors are stacked vertically, allowing more transistors to be packed into the same footprint area without proportionally increasing gate metal process complexity through standardized formation processes.
Solution Approach 2:
The transistor structure is segmented into distinct functional layers including channel layers, barrier layers, and gate electrodes that can be independently formed and optimized. This segmentation allows for modular fabrication where each layer can be processed separately, simplifying the overall gate metal process despite the three-dimensional configuration.
2Manufacturing precision
If silicon germanium cladding layers are grown from sacrificial layers, then manufacturing precision is improved, but process steps increase
Solution Approach 1:
Sacrificial silicon germanium layers are pre-formed at specific positions before the actual channel layers are created. These preliminary sacrificial structures serve as templates that guide the subsequent epitaxial growth of the final cladding layers, ensuring precise alignment and positioning without requiring complex real-time alignment processes.
Solution Approach 2:
The sacrificial silicon germanium layers act as intermediary structures that facilitate the precise formation of the final device structure. These temporary structures enable controlled epitaxial growth and precise positioning of the channel and cladding layers, after which the sacrificial material is removed to complete the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances hole mobility in PMOS devices and allows for the fabrication of three-dimensional integrated circuit devices with increased transistor density while maintaining process simplicity.
Implementation Method 1
epitaxially growing silicon germanium on respective surfaces of each of the silicon germanium layers adjacent the silicon channel
Implementation Method 2
a strained channel, the strained channel comprising a silicon channel and silicon germanium cladding layers on opposing surfaces thereof
Data Source
AI summary
An integrated circuit device includes a p-type field effect transistor that includes a strained channel, the strained channel comprising a silicon channel and silicon germanium cladding layers on opposing surfaces thereof, the silicon germanium cladding layers abutting the silicon channel without being grown therefrom.