SiGe-On-Silicon Pillar Contact Layout for DRAM Plug Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Increasing the plane size of silicon pillars in DRAM cell transistors without altering the pitch arrangement poses a risk of bit-line contact plugs intersecting with cell contact plugs, leading to potential electrical shorts.
Innovation Solution
Incorporating a SiGe layer between the source/drain regions and cell contact plugs, and selectively etching it to prevent contact between adjacent plugs, while maintaining the pitch and ensuring proper insulation and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the plane size of silicon pillars is increased without increasing the arrangement pitch, then the contact margin between cell contact plug and source/drain region is enlarged, but the risk of bit-line contact plug contacting cell contact plug of adjacent silicon pillar increases
Solution Approach 1:
A SiGe layer is introduced as an intermediary material between the source/drain region and the cell contact plug. This SiGe layer is selectively etched to form a recess that prevents the cell contact plug from directly contacting the source/drain region, thereby eliminating the risk of electrical shorting while allowing larger silicon pillar dimensions
Solution Approach 2:
The contact structure is modified locally by forming a recess only in the region where the cell contact plug contacts the source/drain region. The SiGe layer is selectively removed to create this localized recess, while the rest of the silicon pillar structure maintains its original properties, thus achieving isolation without compromising overall device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enlarges the contact margin between silicon pillars without increasing the pitch, preventing electrical shorts and ensuring reliable operation of DRAM devices.
Implementation Method 1
selectively etching it to prevent contact between adjacent plugs
Data Source
AI summary
Disclosed herein is a method that includes epitaxially growing SiGe layer on a silicon substrate, etching the SiGe layer and the silicon substrate to form an active region covered with the SiGe layer, first etching the SiGe layer formed on a first region of the active region without etching the SiGe layer formed on a second region of the active region to form a first trench, and second etching the SiGe layer remaining on an inner wall of the first trench.