SiGe pMOS Transistors with Variable Germanium Concentration
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Solution Overview
Problem
Current integrated circuits face challenges in co-integrating FDSOI pMOS transistors for logic and GO2 transistor circuits without impairing performance, due to limitations in threshold voltage modulation and increased off-state leakage current, particularly in pMOS transistors with high germanium concentration.
Innovation Solution
The method involves forming pMOS transistors with different gate oxide thicknesses and germanium concentrations using a single SiGe deposit, where the pMOS transistor with a higher gate oxide thickness has a lower germanium concentration and a pMOS transistor with a lower gate oxide thickness has a higher germanium concentration, controlled through a condensation process to reduce Gate-Induced Drain Lowering (GIDL) and off-state leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a higher germanium concentration is used in pMOS transistors to reduce threshold voltage and increase current density, then transistor switching speed improves, but off-state leakage current increases
Solution Approach 1:
The patent applies different germanium concentrations to different transistor types within the same integrated circuit. Logic circuit pMOS transistors use higher germanium concentration (e.g., 20-40%) to achieve fast switching, while GO2 pMOS transistors use lower germanium concentration (e.g., 0-10%) to minimize leakage. This spatial differentiation of material composition resolves the contradiction between speed and leakage by optimizing each transistor type for its specific function.
Solution Approach 2:
The patent changes the germanium concentration parameter in the SiGe alloy to independently control threshold voltage and leakage current characteristics. By adjusting this material parameter across different transistor regions, the invention achieves both low-threshold-voltage fast-switching transistors and low-leakage transistors in the same circuit, resolving the trade-off between switching speed and off-state leakage.
2Reliability
If different threshold voltages are achieved by channel doping differentiation, then transistor performance optimization improves, but manufacturing complexity increases
Solution Approach 1:
The patent changes the approach from doping concentration differentiation to material composition differentiation. Instead of varying doping levels in the channel, the invention varies the germanium concentration in the SiGe channel layer. This parameter change simplifies manufacturing because the germanium concentration can be controlled during a single epitaxial growth process, eliminating the need for multiple doping steps and complex process integration.
Solution Approach 2:
The patent replaces the mechanical/doping-based threshold voltage control mechanism with a material-composition-based mechanism. Instead of using ion implantation or in-situ doping to create threshold voltage differences, the invention uses variations in SiGe composition during epitaxial growth. This substitution simplifies the manufacturing process by consolidating multiple steps into a single growth process with compositional control.
3Ease of manufacture
If a single SiGe deposit is used for all pMOS transistors, then manufacturing simplicity improves, but threshold voltage control precision deteriorates
Solution Approach 1:
The patent maintains manufacturing simplicity by using a single epitaxial growth step to deposit SiGe layers across the entire wafer, but achieves precision by controlling the local germanium concentration in different regions. During the growth process, different germanium precursor flows or temperatures are applied to different wafer zones, creating spatially varying germanium concentrations that precisely control threshold voltages for different transistor types while maintaining process simplicity.
Solution Approach 2:
The patent changes the germanium concentration parameter locally during a single epitaxial growth process. By dynamically adjusting the germanium content parameter in different spatial regions or growth stages, the invention achieves precise threshold voltage control for different transistor types without requiring multiple separate deposition steps, thus maintaining manufacturing simplicity while improving precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the co-integration of transistors with optimized performance by reducing off-state leakage currents and achieving balanced threshold voltages, thereby enhancing the overall performance of integrated circuits without severe impairment.
Implementation Method 1
followed by the thermal oxidation of this SiGe layer. During oxidation, the silicon atoms participate in oxidation to form a surface layer of silicon oxide, whereas germanium diffuses into the core of the epitaxial layer
Implementation Method 2
germanium diffuses into the core of the epitaxial layer. The germanium is immobilized between the oxide in the course of formation at the top, and the buried insulator of the substrate at the bottom
Data Source
AI summary
There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon—germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon—germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.